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EDITIONS
MENGIS
This book belongs to: «Vifl4rfW^wwwwv^^^^vv>v v>
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R5 Technical Library
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Basic Microprocessors
and the 6800
BcUSIC
Microprocessors
and the 6800 RON BISHOP Manager, Technical Training Motorola Semiconductor Group Phoenix, Arizona
EDITIONS
MENGIS
Published and Printed with the permission from Hayden Ire.
Book Company,
for Europe, by Editions Mengis, 1981
1979 by
Copyright ved.
No
any form
part of this or
by any
HA YDEN BOOK COMPAGNY,
book may be
means, now known or and recording, or in any inforsystem, without permission in writing from
electronic, mechanical, or other
hereafter invented, including photocopying
mation storage and the Publisher.
retrieval
INC. AN rights reser-
reprinted, or reproduced, or utilized in
Preface
A new device has emerged in
the field of electronics over the past eight
years that will affect the lives of everyone as fifties
and sixties. This
device,
known
much
as the transistor did in the
as a microprocessor,
is
composed of many
thousands of electronic logic elements on one small integrated circuit
less
than
a quarter of an inch square.
As
a result of this
new technology, microcomputer systems
will
be
many homes in
the near future to perform such tasks as controlling lights, storing recipes, recording tax information, maintaining security, and the
included in
like.
Therein
lies
the role of this book.
One
is
able to find
many books about
on the market today. Most of them, however, are aimed at the technical person who has a working knowledge of the subject. A large
digital electronics
majority of them, moreover, cover the high points of three, four, or even five different microcomputer systems. The reader ends up knowing a little about
much about any one system. aimed at several categories of students. If one has a solid digital background but wants to learn about microcomputer systems, he can start with Chap. 7. On the other hand, if he has no knowledge of digital systems covering basic electrical whatsoever, he should start with Chap. 2. Chapter theory, is for the many high-school students and other nontechnical people a
lot
of systems, but not very
This book
is
1
who want
to start at
ing into a study of
,
"ground zero" and learn some electronics before branch-
home computers. This book can
also serve as an ideal text
for colleges, universities,
and technical schools, Each chapter
problems for students to
solve.
Many
offers a set
of
corporations today manufacture microprocessors. Even though
there are differences between brands,
all
microprocessors are very similar
in
a specific microprocessor has beeh mastered, it is very easy to understand other types. In this book, we will focus on Motorola's M6800 microprocessor and the related family of integrated circuits
function and operation,
Once
microcomputer systems. Both the microprocessor and associated family of parts will be treated as a "black box." Although no
that can be used to build its
attempt will be
made
to teach the reader
how
to design a microprocessor,,
he
.
will
how
be shown
sor and
how
it
a microcomputer system can be built using a microproces-
can be programmed to perform the functions desired.
would like to express my appreciation to Ray Doskocil, Bill Johnson, Jasper Norns, Don Aldridge, Dave Van Sant, Brett Richmond, Dennis Pfleger, Ben LeDonne, Clayton Wong, Bob Bratt, Dave Hyder, Jim Ba inter, Lucy Brown, Fritz Wilson, Bill Crawford, Don Jackson, and Donald Kesner, I
each of whom has
made significant contributions much deserved thanks goes to my
to the contents of this book.
wife, Mary Jane, who spent many evenings and weekends typing the manuscript, and special thanks to Chuck Thompon, who has supported our training activities over the past
In addition, a
several years.
Portions of the material in Chaps. 8, 9, 10, and from the following copyrighted Motorola publications:
1
1
2. 3.
1
M6800 Microcomputer System Design Data M6800 Programming Reference Manual M6800 Course Notes
have been reprinted
Sheets
My thanks to Motorola, Inc., for their permission to make use of these documents.
Ron
Bishop
Contents 1
Basic Electronic Principles .1
Voltage
.2
Resistance 2
.3
Current 4
1
A
Kirchhoff's Voltage
.5
Diodes 7
.6
Transistors 7
1.7
Law 5
Example Circuits 10 Problems t2
2 Logic Elements 2.1
22 2.3 2.4 2.5 2.6
2.7
2.8
1
14
"AND" Gate 14 "OR" Gate 15 "NOT" Gate 16 "NOR" Gate 17 "NAND" Gate 19 "EXCLUSIVE OR" Gate 20 Notation 21 Applications 22
Problems 23 3
Number Systems— Why? Numbers 24 Example 25
3.1
Binary
3.2
Digital
3.3
3.6
Base Base Base Base
3.7
Summary 36
3.8
Examples 36 Problems 38
3.4 3.5
25
10 to Binary Conversion 26
10 to Base 8 (Octal) Conversion 28 10 to Base 16 (Hexadecimal) Conversion 31
10 Fractionai Decimals to Binary 35
4 Digital Arithmetic 4.1
Binary Addition 40
4.2
Binary Subtraction 43
4.3
Binary Multiplication 47
4.4
Binary Division 50
4.5
Binary
Coded Decimal 52
Problems 54
40
5 Microcomputers— What Are They?
55
5.1
History 55
5.2
5.5
Computer Model 57 The Microprocessor (MPU) 58 Random Access Memory (RAM) 60 Read Only Memory (ROM) 63
5.6
Input/Output 64
5.3 5.4
Clock 64 Microcomputer System 64 5.8 5.9 Interrupts 65 5.10 Three-State Control 66 Problems 68 5.7
6
7
Programming Concepts 6.1
Flowcharting 69
6.2
Mnemonics 71
6.3
Assemblers 72
6.4
ASCII 72 Problems 73
Addressing Modes
MPU
7.2
Inherent (or Implied) Addressing
7.3
Accumulator Addressing Modes 78 Immediate Addressing Mode 78 Direct Addressing Mode 79 Extended Addressing Mode 79 Indexed Mode of Addressing 81 Relative Addressing Mode 83 Summary 86 Problems 86
7.4
7.6
7J 7.8
7.9
Registers 77
Mode
M6800 Software 8.1
8.2 8.3 8.4
9
75
7.1
7.5
8
69
9.1
88
M6800 Instruction Set 89 M6800 Assembler 131 Sample Source Program 138 Branch Instruction Examples 142 Problems 143
M6800 Microcomputer Family 9.2
78
System Overview 146 Microprocessor Unit (MPU) 147
146
9.4
Random Access Memory (RAM) 162 Read Only Memory (ROM) 163
9.5
Peripheral Interface Adapter (PIA) 164
9.6
Asynchronous Communications Interface Adapter 184 Problems 200
9.3
10
System Configuration 10.1
10.2 10.3 10.4
10.5 10.6 10.7 10.8
11
208
Data Bus 210 Read/Write Line 210 Interrupt Line 210 Reset Line 210 Valid Memory Address 211 Phase 1 (01 ) and Phase 2 (02) Clock 212 Unused inputs 213 Address Lines 273 Problems 218
Example Programs 11.1
11
.2
11
.3
11 .4 11 .5
11 .6
11 .7
219
Add Four Numbers Program 219 Program to Clear Nine Memory Locations 220 Program to Clear Locations 00 Through Hex FF 222 Load Memory with a Data Table (Ascending) 223 Load Memory with a Data Table (Descending) 224
Move $80 Bytes of Data 225 Program to Move a Constant 226 Absolute Values of Two Numbers 227
11 B
Program
11 .9
Multiplication Subroutine 229
11
10 System
to Subtract
Program-BCD
to
LED 231
Machine Control System Program 235 11 .12 Time Delay Program (Short Delay) 241 11 13 Time Delay Program (Long Delay} 242 11 14 Binary to BCD Conversion Program 244 11 15 ACIA Memory Load/Dump Program 246 11 11
Appendix A M6800 Instruction Set Summary Appendix B Powers of 2 and 16
252
!ndex
257
256
1
Basic Electronic Principles
Since
often necessary to interface a
computer with other electrical computer itself, a basic understanding of current, voltage, resistance, diodes, and transistors is necessary. This chapter outlines the basic concepts needed and attempts to avoid nonessential information. Examples are presented to illustrate all principles. circuits
1.1
it is
and devices external
to the
Voltage Everyone has seen the kind of batteries that are used in flashlights, These batteries are a source of voltage. They provide the
radios, toys, etc.
power that generates the current
(or flow of electrons) in a circuit.
Batteries, or voltage sources,
volt automobile battery
is
by hobbyists can be held
in the hand.
types of batteries, other than
A
12- volt battery
together, as
shown
come
in
many
sizes
and shapes.
A
12-
quite large, whereas a 12- volt dry cell battery used
size, is
The primary difference between the two amount of energy they make available.
the
can also be made by connecting eight in Fig. 1.1.
Most batteries purchased
in
1
VI -volt batteries
drug or department
stores for use in flashlights, toys, etc., supply IVi volts.
KDCXZXZDCD 8® 1-1/2 VOLTS =12 VOLTS Fig. 1.1
Connection of eight
1
1
/2-volt batteries
All batteries have a positive (-f) terminal and a negative (— ) termiThese terminals determine how you wire the battery in your circuit. It should be emphasized that the batteries themselves are neither positive nor nal.
Basic
2
The way
negative. is
M icroprocessors and the 6800
the battery
is
wired in your circuit determines whether
it
positive or negative.
The symbol
The
longest line
is
for a battery
(power supply)
is
the positive terminal, and the shorter
line,
the negative
terminal.
Resistance
1.2
When and
a battery
is
connected to a
is
a function of the resistance in that
It
means that anything which
is
called resistance. Resistance (R)
circuit.
limits or
symbolized by the capital Greek often written as 10
circuit, electrons will start to flow,
The amount of current that flows in any
this flow is called current.
is
impedes the current flowing in a
measured
letter
circuit
Now what exactly does this mean?
omega
(H).
circuit
ohms and For example, 10 ohms
in units called
is is
ft.
Resistance values often reach thousands or even millions of ohms. For
convenience, kilo,
it is
common practice to specify thousands of ohms as kohms (for
or 10 3 ) and millions of ohms as
ohms would be written as 3 Mohms. 20,000
Mohms (for mega,
written as 20
Resistance comes in
many
or
10
Step 2:
Draw
the
new
£fi =
1
-
71k
equivalent circuit:
2K
X
-A/VAr
20V_^_
>I.7IK
"I Step 3: Find the total current in the circuit:
20 y
2k Step
4:
+
1.71k
~
20_ 3.71k
_ ~ 539 mA
Find the voltage drop across each resistor: V (across 2k) = 2k (5.39 mA) = 10.78
V
(across 1.71k)
=
1.71k (5.39
mA) =
V 9.22
V
Basic Electronic Principles
7
Notice the voltage drop across the 1.71k (which
4k in parallel with 3k) across the 3k and the 4k resistors. resistance for
The
total current flowing
mA. How much
current
sum
equal to the
the
through the 2k
same
is
resistor in
sum
Example 2
of the currents leaving the junction. Therefore, the
mA. As we
above, the voltage drop across the 1.71k equivalent resistance is
is
5.39
of the currents entering the junction must be
the currents in the 3k and 4k resistors must be 5.39 then,
the equivalent
as the voltage drop
flowing in the 3k and 4k resistors? KirchhofFs
is
current law states that the
is
the voltage drop across each resistor.
By Ohm's law
is
(I
sum of
calculated
9.22 V. This,
=
V/R), the
current in each resistor can be calculated: I (in I (in
4k 3k
resistor)
resistor)
= V/R = = V/R =
9.22/4k 9.22/3k
= =
2.31
3.08
mA mA
+ 2K _ + 20V_=_
5.39
1
mA
2.3lmAl^4K
3.08mAl^3K
"I
1.5
Diodes
It is
symbolized as follows:
The
current flows from the positive (-f) terminal (anode) of the diode to the ( — ) terminal (cathode), as shown by the direction of the arrow. If an
A diode is a device that allows current to flow in one direction only.
negative
attempt
is
made
to
make
the current flow from the cathode to the anode
(opposite the direction of the arrow), nothing will happen.
The through
it.
voltage drop across a diode
In this book,
it
will
is
very small
when
current
is
flowing
be assumed to be zero.
1.6 Transistors
A transistor is a three-lead semiconductor device that may be used in many
ways. In this book,
it
will
be used only as an electronic switch.
Transistors are available in two distinct types called
NPN and PNP,
depending on the makeup of the semiconductor material. The only real difference between an NPN type and a PNP type is the polarity of the battery used in the circuit. Consequently, only the NPN will be discussed.
—
Basic Microprocessors and the 6800 c
>E
Fig. 1.7
The symbol
for
an
Symbol
NPN
for
NPN
transistor
transistor
is
shown
in Fig. 1.7.
Notice the
and E. The B represents the base of the transistor, the C represents the collector of the transistor, and the E represents the emitter of the transistor. These designations are arbitrary ways of identifying the leads coming out of the transistor. Using a transistor as an electronic switch is a very simple process. Only the circuit configuration known as the common emitter will be used in this book. Figure 1.8 illustrates an NPN transistor in the common emitter mode. three leads designated by B, C,
COMMON
EMITTER: The
input circuit
emitter lead
and the output
I
1L
W
100 K
-
+
o
_
IK
wv
B
o-M
+
k
^V
If
5V _ZZ
to both the
circuit.
C
+
common
is
)
^25V
1 Fig. 1.8
To
NPN
transistor in the
calculate the current in
its
common
emitter
base circuit (called the input
the voltage drop between the base and the emitter reality,
V
it is
mode
is
circuit),
assumed to be zero
a very small value). Therefore, the base current,
I B , is
(in
equal to 5
divided by 100k: IB
=
=
5/ 100k
.05
In a transistor circuit such as that
mA
shown
in Fig. 1.8, the collector
found by multiplying the base current, I B by the gain, (called beta), of the transistor. The gain of the transistor can usually be found in the
current,
I c , is
,
A
data sheet that describes the transistor. the typical value
is
assumed
found by multiplying the base current Ic
=
0l B
typical value
=
100
(I B )
by 100:
.05
mA =
X
Recall the rule discussed previously that the in a closed circuit
is
100. Therefore, if
for this transistor, the collector current (I c ) is
must equal the battery
5
mA
sum
of the voltage drops
voltage. In this transistor circuit, the
Basic Electronic Principles
9
voltage drop across the Ik resistor must equal the product of the current through the resistor and the value of the resistor, or V = Ik X 5 = 5 V. Therefore, the remaining voltage of 20 V (battery voltage minus drop across resistor, or 25 — 5 = 20) must be between the collector and the emitter of
mA
the transistor. It is this
The
voltage between the collector and the emitter
voltage that
called
is
V CE
.
of significance in computer circuits.
is
If the 5-V battery on the input circuit were changed to V, there would be no base current (I B ). If there were no base current, the collector current (I c ) would also be 0, which means that the voltage drop across the Ik resistor would be as well. Therefore, the voltage drop between the collector and the emitter (V CE ) must be 25 V since the voltage drops in any closed circuit must equal the sum of the battery voltage. The V CE of 25 volts is known as
the cutoff voltage. collector
A
transistor in the cutoff state has a voltage
and the emitter (V CE ) equal to the battery voltage
between the
in the output
circuit.
On
the other hand,
if
the 5-V battery on the input circuit were in-
(I B ) would be .25 mA (25/ 100k). A base mA would produce a collector current (I c) of /3I B or 25 mA
creased to 25 V, the base current current of .25
(100 is is
X
.25
,
mA). The voltage drop across the Ik
resistor in the output circuit
mA
X Ik, or 25 V. Therefore, the 25 volts from the battery accounted for by the drop across the Ik resistor. Thus, the voltage across
therefore 25
the collector to the emitter (V CE ) of the transistor
is
V.
The
transistor
is
now
in a state referred to as saturated.
A transistor in the saturated state has a voltage between the collector and the emitter (V CE ) approximately equal to V. It should also be noted that any further increases in base current after saturation has no effect on V CE and the output circuit. The maximum collector current possible in the output circuit is the battery voltage divided by the resistance in series with the collector lead. Once the transistor is saturated, the battery and resistance determine the magnitude of the current. As mentioned previously, transistors come in NPN and PNP types. The above discussion was based on the NPN type. Calculations for the PNP type are identical to those for the
NPN
type except that the batteries are
reversed and the currents flow in the opposite direction. Figure 1.9 illustrates
a
PNP transistor using the same size batteries and resistors as the NPN circuit
mentioned
earlier.
_
-vw + 100 K
—
5V~
Fig. 1.9
PNP
transistor circuit
25V
Basic Microprocessors and the 6800
10
were the same as that for the NPN transistor would be of the same magnitude as those in Fig. 1 .8 but their directions would be opposite. Also notice that the batteries (or power supplies) in the circuit of Fig. 1.9 are opposite those in Fig. 1.8. Very often, transistors are shown in a circuit in a slightly different way from that illustrated. The circuit in Fig. 1.8 would be as shown in Fig. 1.10. If the ft of this transistor
in Fig. 1.8, the currents in Fig. 1.9
Fig. 1.10 Alternative
These two
PNP
circuits are identical
transistor circuit
even though they
may appear
quite
an abbreviated way is connected to the 100k would be connected to the emitter resistor. The negative side of the 5-V battery 25-V side of the battery is connected to of the transistor. Likewise, the plus be connected would to the emitter. resistor, negative side the Ik and its different.
In Fig. 1.10, which
thing as Fig.
1.7
1.8,
Example
is
of showing the
just
same
the plus side of the 5-V battery
Circuits
Shown below
are various circuits and calculations of their basic val-
ues.
(a)
iov 2.5
1=
£ 4k
=
2.5
mA
mA
Basic Electronic Principles
11
(b)
20 V
LJ^l
-=-
[p)
S
_=_9V
[p ?3
f2
tl
INPUT TO DIGITAL COMPUTER
Fig. 3.1 Light bulb analogy
It is desired to have the computer monitor the status of the three With all the switches open, none of the bulbs will glow and the voltage to the computer is 0. This will be defined as the logic level. If any switch is closed, the voltage at the bulb will be 9 V, which is defined as a logic 1. Assume that switch 3 is closed; then bulb 3 will glow and the computer will detect a logic 1 on that wire. The status of the input wires changes from 000 to 100, since SI and S2 are still open. Now if S2 is closed, bulb 2 glows, and the input to the computer changes from 100 to 1 10 (assuming S3
lights.
remains closed). If all possible combinations are recorded in a chart, that the three lines to the
computer may have eight
it is
different states, as
below:
db 3 Bulb 2
Bulb
1
Status All bulbs off
1 1
1
1
1 1
1
1
1
1
1
1
Only bulb 1 on Only bulb 2 on Bulbs 1 and 2 on Only bulb 3 on Bulbs 1 and 3 on Bulbs 2 and 3 on All bulbs on
Computer Input 000 001
010 011 100 101
110 111
seen
shown
Basic Microprocessors and the 6800
26
The status of each of the three lines to the computer is in digital form, that is, in one of two states or conditions (1 or 0). The computer can read and record the status of the bulbs and make decisions to do other things based on these inputs.
mind, visualize 16, 20, or even 25 such inputs and consider the problems associated with long strings of l's and 0's if the boss calls and asks for the status of 16 or more individual lines to the computer. Obvi-
With
ously, if
the
it is
l's
very
and
for confusion
3.3
this in
difficult to
0's
convey useful information in
could be arranged in groups of 3 or
4,
digital form.
However,
a great deal of chance
and error would be eliminated.
Base 10 to Binary Conversion
Base 10 number systems have ten distinct numbers, through 9. As one may have guessed by now, since a digital signal must be represented by or a 1, the base 2 number system will play a very prominent role. Base 2 a numbers have only two distinct numbers, and 1. Before a base 10 number can be used by a digital computer, it must first be converted to l's and 0's (that is, into a base 2 number). A method of doing this is known as "repeated division by 2." To illustrate, the base 10 number 29 ]0 will be converted to a base 2, or binary, number. (The number system base is often written as a subscript.) Step 1: Divide the base 10
number by
2:
Remainder
1
14
2)29
Step 2: Divide answer in Step
1
(14)
by
=
1
2:
7
2ll4
Remainder 2
Step 3: Divide answer in Step 2 (7) by
= 0,
2:
Read remainders
3
2)7
Step
4:
Remainder
Divide answer in Step 3 (3) by
3
=
1
=
1
=
1
direction
in
this
to
form answer
2:
1
2)3
Step
5:
Remainder 4
Divide answer in Step 4 (1) by 2JT
Remainder
2:
5
Step 6: Stop dividing when the answer is zero. then read in the reverse order to form the answer:
The remainders
are
Number Systems— Why? 29 10
=111
U
Mir — *
—Remainder
Remainder
29.
(Any number
that 29 10
to the zero
equivalent of 11101, 1
1
we
power
1
1
10°)
+
(2
X
10
1
),
or 9
it
thus 10°
3
Ur 0X2' == 1>1 X
2°
X 1 X »-l X
22
-1
23 24
= = =
J_6
29,o (It checks)
Convert 69, to a binary or base 2 number: 34
R =
2)69
1
17
R =
2)34 8
R =
2717
1
Read remainders
4
R =
2)8
in this direction
2
to
form answer
R =
2)4 1
Therefore, 69 10
2)2
R =
2)1
R =
=
10
1000101 2
.
To
10
1
check: 1,
= 0 1X2 =
UL^l
X
2°
X
2
1
1
=
!
4
X v = X 2 = X 2 = 4 !
1
+
20
=
= 1.) To check the base 2 back to a base 10 number:
is 1;
will convert
4
5
X
really (9
is
1
2
Pat* Remainder 3
I
Remember
Remainder
T_,Remainder
T
1
27
X
26
=
64 69,o (It checks)
28
Basic Microprocessors and the 6800
3.4
0's
Base 10 to Base 8
Conversion
(Octal)
If a base 10 number has been converted to binary, a string of l's and forms the answer. By dividing the l's and 0's into groups and using another
—
—
number to represent each group for example, a base 8 number the total number of digits may be reduced. Base 8 is a very convenient number system for digital computers, as a base 8 number represents three binary digits. To illustrate, the base 10 number of 29 can be converted to its base 8 equivalent in basically the same manner as for base 2, that is, by repeated division by 8. Step
1:
Divide the base 10 number by
8:
3
R =
8)29
Step 2: Divide the answer of Step
5
by
R =
8)3
The base
1
8:
3
answer is obtained by reading the remainders in the reverse = 35 g To check the answer, conversion from base 8 to base 10 is accomplished by multiplying each base 8
order as in a base 2 conversion. Therefore, 29 10 8 digit times
its
.
proper weighted value:
35 8 I
U-5 X
I—^3
X
8°
8
1
= =
5
24 29,
We
have already seen that 29 10
=
(It
checks)
11101 2 Therefore, 29 10 .
=
35 8
=
11101 2
.
between base 8 and base 2 which permits dividing a base 2 number into groups of three digits, with a single base 8 number representing each group. To show this relationship, it will be necessary to convert each base 10 number of 1, 2, 3, 4, 5, 6, and 7 to the equivalent base 2 and base 8 numbers.
There
exists a relationship
Base 10 numbers converted
to
base 2:
610
7,.
3
2)7
3
R
2)6
R =
1
1
2)3
R =
2)1
R
1
T
7 10
=
111;
2)3
R =
1
2)1
R =
1
t
6
=
1102
Number Systems—Why?
2)5
R =
R =
2)4
1
29
1
2)2
R =
2JT
R =
R =
2)2
R =
1
2TT
R =
1
2)2
t
5,o
=
101 2
4 10
=
100 2
t
2 10
=
10,
1
1
1
273
T
t 2JT
R =
1
2JT
R =
1
=
3,
R =
11,
R =
2JT
l,o
=
I2
Base 10 numbers converted
O.o
=
1
2
to base 8:
8)7
R =
7
7,o
=
7,
8)6
R =
6
6,
=
6g
8)5
R =
5
5,o
=
5.
8)4
R =
4
4,o
=
4„
8)3
R=
3
3 10
=
3g
8)2
R =
2
2,o
=
28
8JT
R =
1
l,o
= U
0,o
=
8
Basic Microprocessors and the 6800
30
The relationship of each base 8 and each base 2 number to the equivanumber is shown in the following chart:
lent base 10
Base 8
Base 2
7
7
111
6 5 4
6
110
5
101
4
3
3
100 011
2
2
010
1
1
001
Base 10
000
Notice that each base 8 number has a base 2 equivalent that encompasses three digits of the base 2 number.
What
this really
means
is
that a base
2 number can be divided into groups of three digits each, starting from the right,
and each group may be represented with
previous example, 29 10
=
=01 1
35 g
its
base 8 equivalent. In the
101 2 , notice that the base 2
•
number may
be written directly from each base 8 number or the base 8 number can be written directly from the base 2 number.
1
3
To to base 8
illustrate the
and base
2.
1
1
l2
5,
advantage of this technique, 150 ip will be converted
Conversion to base 8
is
as follows:
18
R =
6
8JT8
R =
2
8)2
R =
2
8J150
1
2
Therefore, 150 J0 = 226 g If the base 2 equivalent is written directly from the base 8 answer, we get 150, =010 110 2 To verify the base J010< 2 answer, let's convert 150i directly to base 2 by repeated division by 2: .
.
75
2)150
R =
37 2)75
R =
1
R =
1
18
2)37
Number Systems—Why?
31
9 2JI1
R=
=
Therefore 150 10
10010110,
4 2l9
R=
1
2 2)4
R =
1
2)2
R =
2JT
R =
1
Notice that this answer and the one obtained by
first
converting 150,0
number and then converting the base 8 number to a base 2 number are identical. The conclusion to be drawn is that for base 10 to base 2 conversions, it is much easier to convert the number to its base 8 equivalent and then to a base 8
write the base 2 equivalent for each base 8 digit. In this last example, three divisions for the base 8 conversion
and eight
it
took
divisions for the base 2
conversion.
This technique also works well in the reverse order. Given a binary
number consisting of many digits, what is the base 10 equivalent? For example, what is the base 10 equivalent number for the binary number 1 101
>
101 2 ?
5
24
320 512 861,
3.5
Base 10 to Base 16 (Hexadecimal) Conversion In the previous section, the convenience of the base 8 system was
illustrated. In this section,
another convenient number system, base
16, will
be studied. The principles of converting from base 10 to any other number
system are the same. However, base
16,
which
the hex system, has a certain mystique about
will hereafter it,
since
be referred to as
some of the symbols
representing the base 16 numbers are letters.
The obvious question one may ask is why use another number system when base 8 works just fine. Most of the microcomputer systems available today is
utilize
up to 16 address
lines.
In the hex system, each group of four digits
represented by one hex symbol. Hence, 16 binary digits can be represented
Basic Microprocessors and the 6800
32
with four hex symbols, or six base 8 symbols. Four hex symbols are easier to
work
with.
In the hex system, the
numbers
through
9,
letters
A, B, C, D, E, and F,
in addition to the
The
are used to represent the hex numbers.
relationship
between base 10, base 16, and base 2 is shown in Fig. 3.2. When counting in the hex system, try to forget that there is a base 10 system. After the number 9 come the "numbers" A, B, C, D, E, and F. This will be the hardest part of the system to understand, but with some practice, it will be as comfortable as
any of the other number systems.
Base 10
Base 16
Base 2
(decimal)
(hexadecimal)
(binary)
0000 1
1
0001
2
2
0010
3
3
0011
4
4
0100
5
5
0101
6
0110
8
6 7 8
9 10
A
7
0111 1000 1001 1010 1011 1100 1101 1110 1111
9
11
B
12 13 14 15
C D E F Fig. 3.2
To
illustrate
by repeated
conversion from base 10 to hex, 156 10 will be converted
division, as in other conversions:
9
R =
16JT56
12
= C
(Remember, 12
R =
16)9
Therefore, 156 10
To applied:
= 9C
convert
in base 10 is
C
in hex)
9
i6 .
9C back 16
to base 10, the
same procedure used
earlier is
1
Number Systems—Why?
33
Cw
9
C X 9 X
16° 16'
= =
12
X
16°
=
12
144 156 10
To
(It
checks)
of the hex system further, the number by repeated division by 2 and then converted to binary by first converting it to a hex number and then to the binary equivalent. Conversion by repeated division by 2 is as follows: illustrate the usefulness
982,0 will be converted to binary
491
R =
2)982
245 2)491
R =
1
R =
1
122
2)245 61
R =
2)122
30
R =
2)61
1
15
R =
2)30 7
R =
1
R =
1
2)3
R =
1
2)1
R =
1
2)15 3
2)7 1
Therefore, 982 10
=
111 10101 10 2 (10 divisions required).
Conversion by repeated division by 16
is
as follows:
61
R =
6
16)61
R =
13
16)3
R =
3
16)982 3
Therefore, 982 10
= 3D6
The next symbol 3,«
=
in the
001
2,
step
16
is
(three divisions required). to write the binary equivalent of each individual
hex number to arrive
D = 16
= D
1101,
and 6 16
at the binary equivalent.
=
From
0110. Therefore, 982 10
Fig. 3.2,
= 3D6 = 16
Basic Microprocessors and the 6800
34
001 11 10101 10 2 Since the 2 leftmost zeros have no meaning, it is common practice to leave them off. Notice the ease in converting a base 10 number to hex and then writing the binary equivalent of each hex symbol. Only three .
divisions are required instead of the 10 needed with the direct way.
The hex system number 1
101
is
1 1 1
to
its
base
also convenient for converting a 16-digit binary
is
10
To
equivalent.
101 100101 2 will be converted to
binary
the
illustrate,
its
base 10 equivalent.
The
number first
from the
to divide the binary digits into groups of four each, starting
step
right,
and write the hex equivalent of each group:
1111
1101
01 10
10
1,
D DF65 16 is the hex equivalent of 1 101 1 1 1 101 100101 The next step is to convert DF65 16 to base 10. 2.
D
F
6 *»
5, —10
L^
X X »-F X -i— D X 5
16°
6
16
5
16 2
16
96 3840 53248
1
3
15
=
13
X X
16 2 16 3
= =
57189,0
Notice the ease in converting the lent.
initial
To illustrate the other technique, we
binary
number
to
its
base 10 equiva-
will convert the binary
number,
digit
for digit, to the base 10 equivalent.
110111110110010 [U: 1,
1
X X X X X X -1 X
^
1
4
1
32
1
64
^oxr ^i -l ^1 ^1 -1
28
2"
256 512 1024 2048
V
4096
V 1
-0 X
2
-1 X
2 14
-1X2
1J
15
16384 32768 57189,
1
Number Systems—Why? It shall
be
35
to the reader to determine the easiest technique for
left
converting base 10 numbers to their base 2 equivalent.
3.6
Base 10 Fractional Decimals to Binary Up
However,
to now, the only
it is
numbers considered have been whole numbers.
often necessary to feed fractional decimal numbers, like .75, into
a computer. These must also be in binary form.
To convert a fractional decimal number into binary form, a method known as "repeated multiplication" will be used. To illustrate, we will convert .75 to its binary equivalent:
Step 1: Multiply fractional decimal number by
2:
.75
X2 1- 050 Step 2:
The
1
or
to the left of the decimal point in step
1
is
part of
the answer. Multiply the remaining numbers to the right of the decimal point
by
2:
.50
X2 i«-(Doo Therefore, since the
answer
is
method
=
zero, .75 10
.11 2
.75,0
To convert that any positive
.
1
2
.
= = =
Now
remember
(7
X
10-')
.7
+
.05
back to base
=
+
part of the
that
X
(5
10" 2 )
.75 10, the
number to the negative power power divided into one): .11 2
when the fractional
stipulates stopping
(1
X
= (1X = (1 X = .5 + = .75,0
2-') Vi) .5)
is
same technique is used (remember the same as that number to the
+ +
+
X
(1
2" 2 )
(^) (1
X
.25)
.25 (It
checks)
appears relatively straightforward, but, in reality, not all fractional decimal numbers will come out so neatly by continuous multiplication by 2. In these situations, it is common practice to continue until the
This
number of
l's
computer.
To
all
and
0's are equal to the
number of individual data lines into the number .3017 10 will be con-
illustrate, the fractional decimal
verted to binary form:
7
Basic Microprocessors and the 6800
36 .3017
.6034
.2068
.4136
X2 ©6034
X2
X2
X2
X2
0.2068
©.4136
©•8272
®.6544
i
i
.8272
i
1
1
1
Therefore, .301 for
many more
10
=
.01001.
.
.
.
As can be
seen, this
multiplications, sometimes never
answer could continue to an end (fractional
coming
part of the answer exactly zero).
3.7
Summary Any
data used by digital computers must be represented in binary
notation. In this chapter, several techniques for converting base 10
numbers
were presented. Also, since data out of the digital computer in binary form, several techniques were presented to convert the l's and 0's
to binary notation is
and written more
into fewer symbols so that they can be spoken
much
easier
write
to
1101 111 101 100101 2 digits).
3.8 1.
the
output
as
DF65 16
than
it
is
easily. It is
to
write
.
These binary digits of l's and 0's are often referred to as bits (binary For example, 11010110 is a binary word consisting of eight bits.
Examples
Convert 1125 !0 to octal (base
8),
hex (base
16),
and binary (base
1125,0 to octal:
8)U25
R =
5
R =
4
17
8)140
1125,0
2
8)17
R =
1
8)2
R =
2
=
2145
8
11 25 io to hex:
70
R =
5
16)70
R =
6
16)4
R =
4
16)1125
4 1125 IO
=
465 16
2):
Number Systems— Why?
37
1125,0 to binary:
= =
1125,o
1125,o
2.
2145 8 465, 6
= 010001 100101 = 010001 100101
2
(Same
2
result either
way)
Convert 782 10 to hex and binary. 782,0 to hex:
48
R -
16)782
= E
14
3
R =
16)48
782,o
f
=
1
R =
16)3 10
to binary:
=
782,
3.
30E 16
=
001 100001 110 2
Convert the following binary numbers to (a)
To
base 16:
To
base
To
base
and decimal.
0110
1011
1100 2
= D6BC,
111
100 2
010
011
=
153274*
10:
D6BC =
(C
= =
12
+ (BX
+ (6 X 16 ) + (D X 16 ) 16°) + (11 X 16 ) + (6 X 16 ) + (13 X 16 ) + 176 + 1536 + 53248
X = (12 X
16°)
16
2
1
3
)
2
1
3
54972,
000101 101 1110101 2
To
base 16:
To
base
To
base 10:
0110
0001
1111
:
0101 2
=
110
101 8
16F5 16
8:
001 16F5, 6
6
8:
101
1
(b)
octal, hex,
1101011010111100,
1101
4.
3
= = = =
011
011
=
13365 8
+ (F X 16 ) + (6x 16 ) + (1 X 16 ) 16°) + (15 X 16 ) + (6 X 16 ) + (1 X 16 ) (5 5 + 240 + 1536 + 4096 (5
X X
16°)
5877,
Convert .528, to binary.
2
1
1
3
2
3
1
Basic Microprocessors and the 6800
38 .528
.056
.112
.224
.448
.896
X2
X2
X2
0.056
@.112
®.224
X2 ®448
X2 ®896
X2 ®792
114
4
4
4
1
1
Therefore, .528 10
=
100001. ... 2
.
Problems 1.
Convert the following base 10 numbers to their equivalent binary, hex numbers: (a)
2
(d) 28
(c) 12
(b) 8
(e)
512
(0 64
(g)
octal,
and
228
(h) 1156 2.
Convert the following base 10 fractional decimal numbers to their equivalent binary numbers:
3.
(a) .505
(b) .444
(g) .7
(h) .99
(c) .715
(d) .325
(e) .95
Convert the following binary numbers to their
octal, hex,
(0 .805
and decimal equiva-
lents:
4.
5.
6.
(a)
110101
(b)
(e)
111101101
(f)
(c)
10101011
(d)
(b)DEF6
In each case below, add
(c) 1
to the
552 (d) 92B number given and
(e)
+ 1 + (c) FF + (d) Ilia + 1 (e) C19 + (a) 99,o
(b) 15 16
1
1
16
l6
1
= = = = =
Convert the following numbers: (a) 48,o
(b) 48, (c) 48,o
(d)
F3 U
(e) 101
2
= = = = =
45FD
(f)
FFF1
write the sum, keeping the
answer in the same number system as the problem:
8.
111111101101
Convert the following binary numbers to equivalent base 10 numbers: (a) 10001011.111 (b) 11000111.011 (c) 11101101.001 (d) 11100111.101 Convert the following octal numbers to decimal numbers: (a) 7521 (b) 33 (c) 677 (d) 463 (e) 555 Convert the following hex numbers to decimal numbers:
(a)F6Dl 7.
11011101 11000111
(binary) (octal)
(hexadecimal) (decimal)
(hexadecimal)
Number Systems—Why? 9. (a)
Express 0111101110000001 2 in both octal and hexadecimal:
Hexadecimal:
Octal: (b)
39
Now
store these
numbers Octal
Which number
in
two
eight-bit locations, using octal
Hexadecimal
system, hex or octal, was easier to use above?
and hex:
Digital Arithmetic
In the previous chapter, methods of converting decimal numbers to binary were shown. Emphasis was put on the fact that digital computers can work only in binary O's and Vs. Now that we have the data in binary, what it? How are these binary numbers added, suband so forth? These are questions that will be answered in this chapter.
does the computer do with tracted,
4.1
Binary Addition
Binary numbers are added just as they are in any other number all of us are most familiar with, the rightmost column of numbers is added. If the total exceeds 9, the rightmost digit of the system. In base 10, the one
sum
is
written
For example,
down and
if
resulting in 13.
the rest of the total
14 and 19 are added,
The
first
is
the 9
carried to the next column.
and the 4 are added together,
down, and the 1 (which represents 10) is which is the tens column. This carry is then the second column, as follows:
3 is written
carried to the second column,
added to the numbers
in
carry
(1) 1
9
1
4
3 3
Binary numbers are added in much the same way. However, it must be kept in mind that the binary system has only O's and l's. When adding binary numbers, four possible combinations exist: (1) (a)
+0
(b)+l
±9 +0
+0
(d)+l
±2
±1
_±i
+1
+1
+10
(c)
carry
In (d), the answer can be verified by converting the answer to base 10: (0
X
2°) -f (1
X V) = 40
+
2
=
2,o
Digital Arithmetic
With
this in
now
mind, we're
If the binary equivalent of 7 10
and
41
ready to do our
binary addition.
first
when converted
are added, the results,
5,
to base 10, will be 12 10 Thus, 111 2 (7 10)
and 101 2
.
(5 10) will
be added:
(C)(B)(A)
111 + The
first
step
is
to
add
1
and
1
1
1
(column A). The
+
1
1
The next step is to add 1 and (column B) A). The result is with a carry of 1:
The next
step
is
column B) are
to the carry of
1
(from column
carry
(1)
+
1:
1
1
1
with a carry of
carry
(1) 1
result is
1
1
1
1
the most confusing, for
to be added.
We must
1 and 1 (column C) and 1 (carry from add just as before, keeping track of the
column as they occur. Thus, 1 -J- 1 is with a carry of 1. Place the carry in the next column, then add the remaining 1 to the just carries in the next
obtained:
carry
(1) 1
+
1
1
1
1
1
Since there are no additional numbers to be added, the last
column C)
is
brought
down
1
(carry from
into the answer:
1
+
1
1 1
1
110 To check
the answer, 1100a
explained in Chap.
11002
is
converted back to base 10 by the techniques
3:
=
(0
=
12 10
X
2°)
+
(0
X
=0+0+4+8 -
2
1
)
+
(1
X
2 2)
+ (1X
V)
Basic Microprocessors and the 6800
42
let's add the numbers 421 10 and 137, in decimal check the binary result by converting to decimal. First, we
To illustrate further, and
in binary, then
convert 421 10 and 137 10 to binary:
421 10 to binary
26 16)421 1
16)26 16JT Therefore, 421 10
cant and
=
may be
1A5 16
=
000110100101 2 (the leftmost zeros are
insignifi-
left off).
137,0 to binary:
8
...
16J137 16)8
Therefore, 137 10
=
89 16
=
I
10001001 2
.
(DO)
R =
Now
add
10 10
-421,0
1
+ 10 10 1110 10 result of
their binary equivalents:
(1)
110 10
The
8
1000101 1 102 or 22E, 6 can
now be
1
-137,0
converted to decimal to verify
the answer:
22E, 6
= = — =
X (14 X
(E
14
+
558,
+ (2 X 16 ) + (2 X 16 ) + (2 X 16) + (2 X 256) + 512 1
16°) 1)
32 (It
checks)
2
Decimal Check 421
+ 137 558,o in performing binary multiplication, 1 + 1 + 1 or 1 + 1 + have to be added. These are added in much the same way except that the number of carries must be carefully determined. To add 1 + 1 + 1, and a 1 in the carry column. Next, the 1 + 1 are first added resulting in remaining 1 is added to the from the previous addition resulting in a 1. Since there was only a 1 carry, it is brought down into the answer:
Often
1
+
1
will
Digital Arithmetic
-fl-j
— *-l + -
+ J +
1
43
= +10
1
+
1
1
11
Likewise,
+ + +
1
•1
+
1
= +10
-1
+
1
= +|0
1
+ 1-
100
1
4.2 Binary Subtraction
The
computers to add binary numbers However, since circuitry to subtract binary numbers is very difficult to design and build, another subtraction method (other than that familiar to us) would be desirable. The method is known as "subtraction by addition of the l's or 2's complements" of the number. is
circuitry required for digital
relatively simple.
The
complement of a binary number is formed by inverting each is, by changing all l's to 0's and all 0's to l's. complement is formed by adding 1 to the l's complement, as follows: l's
binary digit of the number, that
The
2's
Binary number l's
2's
complement complement
= = =
01100100 10011011 10011100
Most computers on the market perform subtraction by "the addition of the 2's complement" of the subtrahend. Subtraction by "the addition of the l's
complement" requires much more hardware to implement. Therefore, we on subtraction by "the addition of the 2's complement."
will concentrate only
tive,
When a subtraction is performed, the answer can be positive or negadepending upon the relative value of the minuend and the subtrahend. We
must, therefore, in some
become apparent
way account
for the sign of the answer.
in later chapters, the data in
most microprocessors
As is
will
repre-
bits. The leftmost bit, called the most (MSB), is used as the sign bit. If the MSB is a "1," the number represented by the remaining seven bits is assumed to be negative and is
sented by eight binary digits, called
significant bit
Basic Microprocessors and the 6800
44 represented by
its 2's
complement.
in the remaining seven bits
If the
positive
is
MSB is a "0," the number represented
and
is
equal to the binary equivalent of
these seven bits. Thus,
1=
1110
L
-Sign bit
+71
16
=
+113,0
=
-109,
=+
or
L
11=
10
10
Sign bit
-6D
16
=—
Let us illustrate by taking a relatively simple example. The number 5,o will is
of
be subtracted from the number
the binary representation of 15,
5,
15,
.
and 00001
,
The 1 1 1
eight-bit is
number 00000101
the binary representation
:
Decimal Subtraction: 15
- 5 + 10 Subtraction by Addition of 2's Complement:
Since the
be represented in
number 5 will be subtracted from the number complement form:
15, 5
must
its 2's
10 =5,o 10 = l's = 2's 1
111110 1
1
+
1
1
1
Ignore'
is
therefore
Included in the ing in detail,
is
L
complement of complement of
1
1111
J0|0 jljl
ljOjO
The answer
1
1
1
5 10
(15)
10 10 10 1
5,o
(5 in 2's
1
complement)
Sign bits
+0A, 6 or +10, M6800 microprocessor, which we will soon be study.
a Condition Code Register containing several bits that indicate (for One of these bits is an
the status of the results of certain operations.
N
Digital Arithmetic
negative)
bit. If the
45
MSB
arithmetic operation sets the of the answer, indicating bit will be set to a "1." Otherwise, it will be a "0."
a negative answer, the
N
The Condition Code
Register also contains a
C
bit. If
the absolute
value of the subtrahend is larger than the absolute value of the minuend, the C bit will be set to a "1"; otherwise, it will be set to a "0." In this last example, both the C bit and bit will be a "0."
N
To illustrate further, let's now reverse the numbers of the first example and subtract the number 15 10 from the number
5 10
:
Decimal Subtraction: 5
-15 -10 Subtraction by Addition of 2's Complement:
1111=
+
1
1
1
1
1
1
1
1
1
IOJ0000 10 l! 1
1
1
Jl',1
1
1
!
t_ Sign
1
is
15 10
complement of complement of
l's
2's
15 10 15,
1
(5)
1
(15 in 2's complement)
=
1
-00001010 2
= -0A, = 4
-10,
bits
In this problem, the in the
= =
N bit and the C bit will be set to a "1." The "1"
MSB of the answer indicates that the answer is negative,
and the value
the 2's complement of the result shown.
As you can
from these two examples, bit 7 serves as the sign bit. number. Thus, the maximum possible positive number is 01111111, or +7F, 6 which is -f-127, Likewise, a "1" in bit 7 indicates a negative number. The maximum possible negative number, represented in 2's complement, is 10000000, or — 80 16 which is — 128, The maximum possible range of numbers is shown in Fig. 4.1, assuming that the
A
"0"
see
in bit 7 indicates a positive
.
,
.
,
data
is
represented in eight
The next
bits.
logical question that
one may ask
is
what happens
if
a
number is subtracted from a negative number. It is possible to subtract (or add) two numbers and obtain an invalid answer. This situation is referred to as a 2's complement overflow. In addition to the C and N bits just described, the Condition Code Register also contains a V bit. When a subtraction (or addition) is performed and a 2's complement overflow occurs, the V bit will be set
Basic Microprocessors and the 6800
46
Number in 2's
Hex equivalent number
Binary equivalent
complement
number
0111 1111 (7F) 0111 1110(7E) 0111 1101(7D)
•
•
•
•
0000 0010 0000 0001 0000 0000
1111 1111(FF) 1111 1110(FE)
-0000 0001 -0000 0010
•
7D
•
0000 0010(02) 0000 0001(01) 0000 0000(00)
01
00 .
must already be
-1
-02
-2
•
•
•
•
-7E -7F -80
-126 -127 -128
Maximum
will
it
-01
•
Fig. 4.1
number 45 (69 10) from
•
+2 +1
-0111 1110 -0111 1111 -1000 0000
•
to a "1"; otherwise,
•
02
•
1000 0010(82) 1000 0001(81) 1000 0000(80)
+ 127 + 126 + 125
7F 7E
0111 1111 0111 1110 0111 1101
•
Decimal equivalent
possible range of numbers
be cleared.
To
illustrate, let
us subtract the hex
number —60 (— 96 10). The minuend complement representation:
the hex
in the 2's
(
— 96
10)
Decimal Subtraction:
- 96 - 69 — 165
(outside of allowable range)
Subtraction by Addition of 2's Complement:
10 10 11111 10 10
60 16 )
1
10 10 10 1110 10 10 1110 11 1
+
1 's
2's
l's
2's
,
60i 6 )
2's 2's
complement of 45 16 ) complement of 45 16 ) complement of 60 16 ) complement of 45 16 )
the addition of the 2's complement resulted
an answer of +5B l6 which is +91 10 Therefore, the "1" since the answer should be — 165 10
in
60i 6 )
:45 16 )
10 10 10 1110 11 10 10 110 11
The above subtraction by
complement of complement of
.
.
V
bit will
be
set to
a
47
Digital Arithmetic
4.3 Binary Multiplication Binary multiplication
is
quite similar to decimal multiplication. If the
decimal numbers 16 and 12 are multiplied, the 6,
first
step
is
to multiply 2
X
resulting in 12:
carry
(1)
16
X
12
2
The
2
is
carry of
1, which is the ten's unit (12 = 10 4- 2), is shown above. Then 1 is multiplied by 2, and the
written down, and the
carried to the next digit, as
from the
1
first
multiplication
is
added to the
result:
16
X12 32
Then one
the 6
is
multiplied by
1,
and the answer,
6, is
placed under the 3 (shifted
digit to the left):
16
X12 32 6
After multiplying
1
by
1
and placing the
previous step, the final answer
is
result, 1, to
the
left
of the 6 from the
obtained by adding the partial results: 16
X_12 32 16
192 Just as a multiplication table has to be learned for the decimal system, a
multiplication table for binary
numbers must
0X0
also be
memorized:
=
0X1=0 1X0 = 1X1 =
As can be
seen, this multiplication table
is
1
much
easier to
remember than the
decimal multiplication table drilled into us in our early school days.
1
1
1
1
Basic Microprocessors and the 6800
48
To
illustrate the ease
with which binary numbers can be multiplied, ) used in the previous example will be used
the same two numbers (16 10 and 12, again:
16,o
12 10
= 10000 = H00
2
2
10000
X
1100
00000 00000 10000
10000 11000000 2 This
a relatively simple example, since there are
is
principles are the same.
1
To
no
carries,
1000000,
= (1 X 2 ) + X = 64+128 = 192, (It checks) 6
*(1
2
7
)
Let us look at another example. The binary numbers 10
be multiplied. In decimal notation be
15,
but the basic
check:
this
would be
5,
X
3,
,
2
which
and is
1
2
will
known
to
.
Step
1:
101
x_n 101
(1
X
101
=
101)
(1
X
101
=
101)
Step 2: 101
X_il 101
101
Step 3:
Add
partial results:
101
x_n 101
+ 101 1111 2 Therefore,
1 1 1
2
=
15,
.
A more difficult example, ries, is 1 1 1
2
X
illustrating binary multiplication
111 2 In decimal, this .
would be
15 l0
X
7,
,
with car-
or 105,
.
49
Digital Arithmetic
1111
X
111
1111
+
1111 1111
In adding these partial results, one must be very careful:
Step 1: Bring the rightmost
down
1
as part of the answer:
1111 1111 1111 1
Step 2:
Add
the
and
1
1,
with a carry of
resulting in
1:
(1)
dXi) 1
1
carry 1
(1)
1111 1
1
1
1
1
1
Step 3: There are
carry
1111 1111 1111
1
now
four
l's
added to form the next part of with a* 1 and 1, resulting in resulting in 1; and finally, adding
to be
the answer. This can be thought of as adding
carry of
1;
then adding the next
the last
1,
resulting in
Step 4: Similar to step 1
with two
to the 0,
1
with another carry of
Adding
3.
+
1
1
(two
carries):
1
+
+
1
1
+
1
results in a
carries:
(1)
(1)1
1
1
1
1111 1111 10 Step 5:
Same
as step
3(1
+
1
+
1
+
1
(1)
1111
(1)1
1
1
1
1111 10
1
1=0 with two carries):
Basic Microprocessors and the 6800
50
Step
Add
6:
+
last three i's (1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
1 1
Checking the
+
1
1
1
1
=
with one carry):
1
12
result:
1101001 2
= = = =
69 16 9
X
16°
9
+
96
105io
+
(It
6
X
16
1
checks)
Multiplication with digital computers
is
often accomplished with the
program in memory rather than the hardware itself. The theory and basics just covered are implemented by the program to perform a binary multiplication. As was just explained, binary multiplication is nothing more than a series of shifts and adds of the multiplicand. A multiplication program shown in Chap. 11 illustrates these principles.
4.4 Binary Division Binary division division.
The
is
accomplished in nearly the same way as decimal
division table
is
very simple:
Meaningless, just as
it is
in
the decimal system \
To illustrate binary division, the number 18io
=
100102 and 6 10
=
110, the
problem
is
1
8 will
be divided by
6.
Since
written as
110)10010 Step
1:
Therefore, 110
Since 110
is
is
larger than 100,
divided into 1001.
it
will not divide into 100.
Digital Arithmetic
51
1_
110)10010 110 11
Subtracting 110 from 1001 can be thought of in the following way. What number, when added to 110, will equal 1001? Obviously,
+
11
Step 2: Bring
down
=
110
1001
and divide
the last
again, just as in the decimal
case:
11
110)10010 110 110 110
The answer,
11 2 , checks with the
Very often problem
is
illustrate,
in division, the
handled in
2710
will
much
known answer answer
same way
the
be divided by 4 10
.
First,
as
of 3 10
come out even. Again,
it is
in the
16JT
27 10
=
Since 4 10
Step
=
1B 16
R =
11
R =
1
=
= B
0001 101
100 2 the division proceeds as follows: ,
1:
1_ 100)11011 100 101
Step 2:
n_ 100)11011
100 101
100 1
decimal system.
we must convert 27 10
1
16)27
.
not
will
2
this
To
to binary:
Basic Microprocessors and the 6800
52
Step 3:
110
100)11011
100 101
100 11
Step 4: 110.1
100)11011.0
100 101
100
110 100 10
Step 5: 110.11
100)11011.00
100 101
100 110 100 100 100
To
convert
methods of Chap. 110.11 2
= = = =
1
10.1
2
to the decimal system as a check,
X 2" ) + (1 X 2' ) + (0 X 2°) + (1X + 2 + 4 (1 X U) + (1 X Vi) + 4 .25 + .5 + 2 2
(1
we
use the
3: 1
2
1
)
+
(1
X
22)
-(-
6.75,0
(It
checks)
Again, as in multiplication, division is usually accomplished in digital computers with a computer program (to be discussed later) rather than with electronic circuitry. However, the principle just discussed must be understood if the computer program is to be understood.
4.5 Binary
Coded Decimal
Another method of representing numbers in digital computers is known as binary Coded Decimal (BCD). In the BCD system, each decimal
,
Digital Arithmetic
digit
is
represented with
would be represented
It
its
in
own binary equivalent number. For example, 743
BCD
as:
0111
0100
0011
7
4
3
BCD
must be emphasized that
example, 49 10 in binary
Many
53
is
devices use
110001 2 but in ,
BCD
and binary are not the same;
BCD
it is
for
01001001.
format for data transmitted and received.
we must know how to handle this data. Adding numbers in BCD can cause problems if we are not fully aware of the possibility of invalid results. To illustrate, let us add the numbers 60 10 and 55 10 in BCD: Consequently,
60,o 55,o
= =
0110 0000 0101 0101 1011 0101
As you can see, the answer is invalid since 101 1 is not a valid BCD number. We know that the decimal answer is 115. Therefore, a correction must be made. Notice what happens when 60 is added to the above result: 1011 0101
1
0110 0000 0001 0101
1
We now
1
5
have the correct answer, 115. The
instruction
(DAA)
that will
M68OO
Microprocessor has an
make whatever adjustments
are necessary to
correct an invalid result.
A
"Binary to BCD Conversion" program is presented in Chap. 11. This program takes binary numbers and structures them into the BCD format:
Decimal number
BCD representation 0000
1
0001
2
0010
3 4 5 6 7
0011
8 9
0100 0101
0110 0111 1000 1001
Basic Microprocessors and the 6800
54
Problems 1.
in decimal).
Perform the following additions in binary (numbers given are Verify the results in decimal.
9
(a)
-
3
17
(d)
(0
-42
73 33
-U
Perform the following multiplications in binary (numbers given are mal). Verify your answers in decimal. 5
(a)
X
123
(e)
X
12
(b)
X6
5.
-
5
50
(e)
-16
4.
+642
Perform the following subtractions (numbers given are in decimal) by "addition of 2's complement." Verify your answer in decimal. (c) 142 26 (b) 10 (a)
-
3.
178
(0
+22
+ 128 2.
72
4-
16
(e)
158
(c)
+21
128
(d)
28
(b)
+3
X
8
12
(f)
125
(d)
X
2 8
(g)
(h)
X4
X12
12
13
(c)
in deci-
3
17
X17"
Perform the following division in binary (numbers given are in decimal). Verify your answers in decimal. (a)
6)36
(b)
6)40
(c)
8)46
(d) 26)78
(e)
24)108
(f)
25)179
(g)
3)47
(h) 7)60
(i)
10)l05
Show
the following decimal numbers in binary and
BCD:
(a)
9
(b)
13
(c)
42
(d)
92
(e)
103
(0
783
(g)
1243
(h)
9436
Microcomputers— What Are They? At
this point,
we've learned
binary numbers (l's and
O's);
how
how
to convert decimal
numbers to
binary numbers can be added subtracted,
and divided; and what logic elements are. Where does all this fit computer system? What can a computer do? How does a computer work? How does it know what to do? Does it think for itself? These are some of the questions that will be addressed in this chapter.
multiplied, into a
5.1
History
ago,
is
Computers are not new. The abacus, which originated many centuries a form of digital computer. This calculating device, illustrated in Fig.
can be used to add, subtract, multiply, and divide. Each column contains two beads above the crossbar and five beads below it. Each bead above the cross bar represents five units, and each bead below it represents one unit. 5.1,
Notice the value of each column as shown below the abacus. The number depicted is 10201. If the number 60201 were to be illustrated, a bead above
column would also be raised. Details of "abacus shown here. However, with a little imagination, partic-
the cross bar in the 10,000
arithmetic" will not be
F==i
100,000
F==l
10,000
»===»
1,000
Fig. 5.1
P^
A
100
10
Abacus
55
»==»
I
Basic Microprocessors and the 6800
56
on number systems, one can understand
ularly after reviewing the chapters
how
the abacus
The
a form of computer.
is
first
mechanical adding machine was developed in the 1600s.
Several other types of adding machines and various rudimentary forms of
computers were invented over the next 350 years. In the late 1940s, the "electronic" computers were introduced, but they used vacuum tubes. Such tubes were not really the answer, since they are quite large (1 to 3 in.
digital
first real
high), require large
amounts of power
as well as space,
and generate tremen-
dous amounts of heat.
With the invention of the late
1940s and early 1950s,
many
solved. Transistors are small relatively little
power. They
transistor, a
compared
and require and build digital comcabinets and racks that would easily fit in a
made
puters which could be housed in
semiconductor device, in the
of the problems associated with tubes were
it
to tubes (V4 in. high)
possible to design
modestly sized room.
With
Then in the late 1960s and early new technology, we were able
this
was born. module containing 5 to
1970s, the microprocessor to replace a
10,000 transistors with a small piece of semiconductor material less than
term microprocessor. Although the basic principles little, this small chip of semiconductor material, often referred to as an "integrated circuit," opened the door to a whole new era of microelectronics. New computer-controlled applications that were beyond our wildest dreams several years earlier now started to emerge. Hand-held electronic calculators a luxury item for the average person only several years ago are now available to everyone. Electronic TV games, such Va -inch square; thus, the
of digital computing changed very
—
—
as ping-pong, are also a by-product of the microprocessor.
The
list is
"MPU" and "MICROPROCESSOR": These terms are used
endless.
inter-
changeably.
impact
Even though the microprocessor has already affected our lives, its full yet to come. By 1985, a large number of homes in the U.S. will have
is
some kind of computer-based system
containing, in
all
probability, a micro-
processor. These microprocessor-based systems will control lights, pool
mo-
monitor a security system, keep tax records, store recipes, and so forth. The only limitation is one's own imagination. Functions previously performed by computers costing thousands of dollars in the 1960s can now be handled by a microprocessor-based system costing less than $1,000 and occupying much, much less space. A microcomputer kit, which can be assembled in less than 10 hours, can be purchased for less than $200 today. tors,
We
are indeed entering a
new
era.
Microcomputers—What Are They?
57
Computer Model
5.2
Before the microcomputer system
develop a computer model to illustrate
is
studied in detail,
let
us
first
its basics.
Picture yourself sitting at a large desk.
The
shirt
you are wearing has
a pocket on each side. To your left is a stack of cards, face down, each with an instruction printed on its face. To your right is a small blackboard, a piece
of chalk, and an eraser. Directly in front of you are two trays, an input tray
and an output
tray.
On
We have now puter system. You
the wall
is
a large clock.
created a a situation which
will act as the
MPU. You
is
analogous to a microcomdeck of
will pick a card off the
cards once each minute and execute the instruction printed on
deck of cards can be referred to as a "Read Only contents cannot be changed. Each card in this
its face.
Memory" (ROM),
The
since
its
ROM represents an "instruc-
memory. The blackboard, chalk, and eraser to your right may also be referred to as a type of memory. However, in this memory, you can write things down and erase them later on. Such a memory can be referred to as a "Random tion" in
Access
Memory" (RAM),
since
it
may
be written on or changed at random.
can be used for storing data (writing information). Time (each minute) will be determined by the clock on the wall. Any operation performed by you (the MPU) must be done in an orderly, timed It
sequence.
The two
trays in front of
Information to you (the output from the system,
to write
you are the "input" and "output"
MPU) must come through
trays.
the input tray. Likewise,
MPU must go through the output tray. The input tFay, in this
with cards containing random numbers from 1 to 10. The pockets in your shirt each contain a sheet of paper large enough one number on and a pencil with an eraser. Your left pocket may be
is filled
"A
RAM
An
accumulator is similar to the can hold only one number whereas can store several numbers. Your right pocket may be referred to as the your "B accumulator." Both accumulators are identical and perform identical functions, that is, providing temporary locations for the storage of numbers.
referred to as an
accumulator."
(Random Access Memory)
except that
it
RAM
program (ROM) will direct you (the MPU) by the addition of numbers from the input tray, five odd numbers greater than 100 on your blackboard (RAM). The instructions on the
The
instructions in your
to accumulate,
first
eight cards read as follows:
Card
1:
Card Card
2: 3:
number on
the
Is the number odd? If yes, skip cards 3, 4, and 5. Read a number from the input basket and write this number on
the
Read a number from the input basket and write paper in your left pocket (A accumulator).
paper in your right pocket (B accumulator).
this
—
58
Basic Microprocessors and the 6800
Card
Add the numbers from your right and left pocket and put the result
4:
on the paper in your left pocket. Is the number odd? If not, go back to card 3. Is the number greater than 100? If not, return to card 3. Write the number located in your left pocket on your blackboard. Are there five numbers on your blackboard? If not, return to card 1.
Card 5 Card 6 Card 7 Card 8
—the program —
Just as an instruction from your deck of cards
ory
—
(ROM)
mem-
in
MPU
read and executed by you in sequence (unless you the are told to branch to some other instruction) during some time interval, so does a microcomputer system execute its instructions. In our analogous sys-
—
is
is stored in temporary locations (pockets and blackboard). A microcomputer system also contains temporary storage locations, called accumulators and RAMS, that function in much the same way. Microcomputer
tem, data
systems also have a clock to control the sequence of events, and the input and output trays of our model system are similar in function to those of a mi-
crocomputer system. Notice that as each instruction is read, you must either make a logical decision based on the contents of the instruction or perform some calculation. These actions are the function of the microprocessor in a microcomputer system. However, in the latter, the instructions have to be coded in some manner. Remember that digital computers respond only to a binary (l's and 0's) language. Therefore,
each instruction
in
our analogous system must be
represented by a binary number. For example, card 4 might contain the binary interpreted by the MPU as "add the A accumulator to the contents of the B accumulator and put the A accumulator."
number 0001 101 1 (1B 16 ), which would be contents of the the results in
As you probably have concluded by this time, a microcomputer system consists of five elements: (1) a microprocessor (MPU), (2) a random access
memory (RAM),
(3) a read only memory (ROM), (4) a clock, and (5) some technique for getting data in and out of the system (input and output).
5.3
The Microprocessor (MPU) The
in the
hand, yet trol,
role of a microprocessor chip
computer model just discussed.
and
it
contains
all
It is
it
analogous to the role you played it
can be held in your
the electronics necessary to perform arithmetic, con-
logical functions. Since the
devices in the system,
is
so small that
MPU
must communicate with other to decide which one of them "address." This problem is solved
must have some way
—
RAM, ROM, input, output it wishes to by attaching several wires, called lines, to each device these lines "address" the device the
in the system. Since
MPU wishes to communicate with,
are referred to as an "address bus."
Most
MPUs
they today contain 16 address
Microcomputers—What Are They? lines.
By charging some of them
low voltage
at
an address
(logical O's)
59
a high voltage (logical is
generated.
The
l's)
and some
at a
device with that address
communicate with the MPU. (Multiple device addressing will be 10.) For example, consider the 16 lines (wires) that make up the address bus in Fig. 5.2. Assume that we wish to communicate with a device whose address is 832 16 The binary pattern of 832 16 is 1000 001 1 0010 0001. If each line that represents a "1" in this binary number were charged at 5 V and each line that represents a "0" were charged at V, only one device at the other end of these wires (bus) would answer to that address and communiwill then
covered in Chap.
.
cate with the
MPU.
lead from the
MPU in the direction of the devices, thereby indicating that all
Notice that the arrows of the address bus in Fig. 5.2
addresses are generated by the
numbered
through
MPU.
all
Notice also that the individual lines are
Since each line will have either a high or low voltage to represent a binary "1" or "0," the lines will be collectively referred to as "bits," a
15.
term derived from the words binary
referred to as "16 bits." Standard practice
when
significant bit 1,
and so on
treated as a binary
to the sixteenth line (the
binary number), which
is
is
digits.
The 16
to refer to the
lines, then,
first line
are
(the least
number) as bit 0, the second line as bit most significant bit when treated as a
referred to as bit 15. It
is
also
common
practice to
a group of eight bits as one "byte." Therefore, the address bus of 16 wide would be two bytes wide. Bits through 7 make up the least
refer to bits
significant byte,
and
bits 8
through 15 make up the most significant byte (see
Fig. 5.3).
Just as the cate with,
it
must
MPU must address the device that
also have
or receive data from, the device after
you
dial
it
some channel through which
wishes to communiit
can send data
to,
when must be some way of
has been addressed. Similarly,
it
an address (number) on your phone, there
sending and receiving data (talking and listening). In a computer, this transaction takes place
on a
series
of wires (lines) referred to as a "data bus." Most MPU CONTROL
DATA BUS
CONTROL FUNCTIONS LOGICAL FUNCTIONS ARITHMETICAL FUNCTIONS
BUS
DEVICE
Y
AD0RESS BUS
Fig. 5.2
MPU
Basic Microprocessors and the 6800
60 15
14
13
12
9
10
II
7
8
6
4
5
2
3
I
UUJUUHUlU —
L—
I
J-
BYTE
BYTE LEAST SIGNIFICANT BYTE I
MOST SIGNIFICANT BYTE v^_
BIT*'*
J >
..
Y AODRESS BUS
Fig. 5.3
Address bus
MPUs today use a data bus consisting of eight data lines (bits) although there some MPUs with 16 data lines. Notice the doubly directed arrows of the
are
5.2, indicating that data can be sent or received by the MPU. Again, a high voltage on a data line indicates a binary "1," and a low voltage
data lines in Fig. indicates a "0."
The
third type of microcomputer "bus"
is
the "control bus." Its lines
control the sequence of events for the total system. For example,
data on the data bus,
is
whether the
MPU
store the data
is just
it
is
when
there
the job of the control bus to inform a device
trying to get data from
on the data bus, that
is,
or whether the device should
it
whether
it
should "read" or "write."
Several separate functions are performed by the control bus of any microcom-
puter system, varying from one type of microprocessor to the next. These differences will be discussed in detail in
Chap.
9.
As was shown in our model, the MPU must provide areas for temporary storage of data. Some MPUs have one accumulator, but many have two or more* The system we will be studying in Chap. 9 uses two accumulators, an
A
accumulator and a
B
accumulator. Accumulators are often referred to
as "registers," for example, the
Other index will
registers also
register, the
A
register or the
found
stack pointer
register,
B
register.
program counter, the and the condition code register. These are the
MPU.
Random Access Memory (RAM) As was
is
MPUs
be discussed in detail in later chapters, since their characteristics are often
a function of the individual type of
5.4
in
illustrated in the
an area where data
may
new data stored in its place. The data bus in Fig.
MPU.
computer model presented
be stored; this data
5.4
is
the
same
may
earlier,
a
RAM
be erased at any time and
as that
shown
in Fig. 5.2 for the
marked SI, marked A0 through A6. It is through these sets of lines that a RAM memory location is addressed. The function of the "chip select" might be compared to selecting a page in a book whereas that of the "word select" might be compared to selecting a line on that S2,
In this simplified example, notice the three "chip selects"
and
S3.
Also notice the "word select"
lines
Microcomputers—What Are They?
61
RAM DO Dl
WORD
02
SELECT
03
DATA BUS
TO/FROM MPU
D4 D5
06 07 S3
S2
SI
TTT CHIP SELECTS
Fig. 5.4
RAM
and "word selects" are means of specifying an These lines will therefore be connected to the address but a set of rules must be observed to achieve the desired
page. Both "chip selects"
RAM.
address on the
MPU,
bus from the address.
and a low As you can see, then, the address of a RAM is determined by the way SI, S2, and S3 are connected to the address bus. For example, if SI and^2 were connected to bit 14 and bit 15 of the address bus, respectively, and S3 were connected to bit 13, the address of this RAM would be 1 100 0000 0XXX XXXX. (The assumption is made that this address is for one device only.) The X's shown in the address will be connected to the word select lines to address an individ-
When a high signaj_("l") is applied to SI and S2 of Fig.
signal ("0")
ual
word
is
applied to S3, this particular
in this
5.4
RAM will be addressed.
RAM.
Since there are seven
word
select lines, the
number of words
that
may
RAM
range from 000 0000 (all lines with volts) to 1 1 1 1111 (all lines to a high voltage). This binary range is equivalent to 00-7F (base 16), which is the same as 128 locations. As you probably have
be addressed on
this particular
RAM
is eight bits (one by now, the data word length acceptable to the which can be put directly on the data bus. is illustrated in Fig. The relationship between the MPU and the 5.5. The R/W line shown is a signal line from the MPU to inform external devices that the MPU wants (1) to read data, if this line is high, or (2) send
realized
byte),
RAM
(write) data, if
it is
low.
To expand on the word selection the chip selects and in Fig. 5.5. If
A0-A6
word
RAM, let's assume that
MPU
address bus as shown
A 14 and A15 are put in a high state and Al 3 in a low state while
are in a low state, the contents of
gated to the data bus
R/W
process of a
selects are tied to the
line will
if
be high).
memory
location
000 0000
will
be
MPU requests the contents of that location (the If the MPU desires to read the contents of location
the
—
62
Basic Microprocessors and the 6800 MPU
RAM
^
AO
DO «*
Al
Al
01
A2
^- A2
A3
A3
A4 A5
A4 ». A5
D4 D5 -*
A6
»> A6
06 TO AND FROM ^MPU *>
03
J
R/W S3
_A
AI3
S2
SI
n
n
AI4 AIS
Fig. 5.5
001
1
A15
A5
01
1 1
will
(37 16 ), the
be high and
MPU
connections with
RAM
R/W line will be in the high state; address lines A14 and A13
will
be low; and address lines AO, Al, A2, A4, and
The contents of this location would then be placed on the data bus to be transferred to the MPU. will
be high (see Fig.
5.6).
37 1C
«
I
I
I
I
L
AO (HIGH) Al
(HIGH)
A2 (HIGH) A3 (LOW)
A4 (HIGH) A5 (HIGH) A6 (LOW)
Fig. 5.6
Memory
location
37 1{
for this RAM, as it is presently connected to 100 0000 0000 0000 (location 000 0000 of this RAM) 100 0000 01111111 (location 1 1 1 1 1 1 1 of this RAM), or from C000 16 to
The range of addresses
the address bus, to
1
C07F 16
from
1
.
It
to
is
should be obvious by
now that
all
AO's through A6's would be tied
AO through A6 of the address bus if there were more than one RAM in the
system. However, chip select lines SI, S2, and S3 would be tied to different will
RAM
with its own unique address. This matter be covered in greater detail in Chap. 10. The we have just considered has 128 memory locations, each
address lines to provide each
RAM
RAMs vary from 1024 bits each to 16,384 However, the principles discussed are still applicable.
eight bits wide. Other types of
each.
bits
Microcomputers—What Are They?
63
RAMs come in two basic types, referred to as static and dynamic. Dynamic RAMs usually have more storage capability than static RAMs since their storage cells are smaller. However, what is known as a "refresh signal" must be applied to the
signal. its
their cells as frequently as once every millisecond, or the This signal often comes from the clock, which causes
MPU MPU to run at a slightly slower rate. Static RAMs do not need this refresh
data will be
lost.
As long as the main power source is applied,
the static
RAM will retain
data.
5.5
Read Only Memory (ROM) Read only memories (ROMs) have an address scheme much the same RAM. The program to tell the MPU what to do is stored in
as that of the
but the MPU cannot change the contents RAM locations. Programs are fixed in ROM memories by several different techniques.
consecutive locations in the
of
ROM
One
locations as
it
ROM,
can
"mask programmable." After a user has written his program, he ROM manufacturer. The manufacturer will then produce the ROM, usually in large quantities, with the program built in. ROMs obviously do not need to have power continually applied or to be refreshed to hold their is
called
supplies
it
to a
ROM
program. This state is referred to as "nonvolatile." A typical containing 1024 separate locations, each eight bits wide (1024 X 8), is shown in Fig. 5.7.
ROMs
vary in size just like
RAMs. ROM
DATA
BUS FROM
MPU
00
AO
01
Al
02
A2
D3
A3
D4 05
A4
D6
A5 A6
07
A7
ADDRESS BUS FROM MPU
A8 A9 CS
CS
CS
CS
TTT1 Y *CHIP selects TIED TO
*THE CHIP SELECTS ARE DEFINED BY THE USER ASPOSITIVE (CS) OR NEGATIVE (CS)
ADDRESS BUS
Fig. 5.7
ROM
Notice that the data lines are directed toward the only from the
MPU. Data can flow
ROM to the MPU. As one can see, the required ROM must be
Basic Microprocessors and the 6800
64
selected by the proper signal on the chip selects from the address bus, after which the individual memory location must be addressed through AO-A9 of the address bus. The addressing scheme will be covered in detail in Chap. 10.
5.6 Input/Output All microcomputer systems must provide a way of getting data loaded and out of the system, usually by means of one or two chips called I/O ports or peripheral interface chips. The program can then direct the MPU either to read the status of the input lines on these chips or to send some data into
to their output lines.
The
be discussed in Chap.
5.7
details of the
I/O chip
for the
M6800
system will
9.
Clock
Just as the computer model developed earlier depended on the clock on the wall to determine when events were to happen, all microcomputer systems are also regulated by clock signals. These signals are routed through in a timely, orderly the MPU to allow it to execute instructions from the manner.
ROM
5.8
Microcomputer System It is
now
time to consider
all
the computer elements discussed in this
chapter as they relate to the overall system. This interrelationship Fig. 5.8.
ADDRESS BUS
RAM
u
(16 BITS)
l
MPU
ROM
+ /
i
""-DATA BUS (8 BITS)
INPUT
j
CLOCK
OUTPUT
Fig. 5.8
Microcomputer system
is
shown
in
Microcomputers—What Are They?
65
that the MPU does only what the program in the ROM A common misconception many people have is that computers
Remember directs
it
to do.
are superbeings, that they have brains and can "think." That belief, of course, is false,
you already know. They do exactly what they are told to do and it very fast. The contents of two accumulators can be added in 2 or 3 microseconds (.000002 sec). That's fast!
as
only that, although they do typically
5.9 Interrupts In the control bus to and from the lines is called
an "interrupt
line."
MPU shown in Fig. 5.2, one of the
This section will
purpose of
illustrate the
"interrupts."
which the primary duties so that it may perform a task much more important. The MPU may be monitoring some rather routine input lines, doing calculations, storing data, and the like, when an emergency type situation occurs. When the is made aware of this Interrupts, as the term indicates, refer to a technique in
microprocessor
is
interrupted from doing
its
MPU
emergency situation by an interrupt, executing, stores the contents of
program
its
it
finishes the instruction
internal registers,
and goes
it is
to
presently
an internal
to solve the difficulty.
Before essential to
we can
obtain a thorough understanding of interrupts,
understand what a "real time computer system"
familiar with the
many hand
it is
We're
all
calculators available. These calculators just
sit
is.
around until you need them, at which time you punch in some numbers, perform some arithmetical calculations, and read the results in the display. A "real time operating system" is similar to the calculator, except that data is continually being fed into the MPU and compared against known data so that output decisions can be made.
To extend the illustration, let us create a "real time situation." The automobile that you have just purchased has a microprocessor system that controls and monitors the following functions: 1.
Sounding an alarm
if
water temperature
rises
above a certain
predetermined limit 2. 3.
Maintaining speed at a value you select Maintaining the interior temperature at a value you
select.
In reality, it could, and would, perform many more functions, but for the sake of simplicity, these will be enough to illustrate a "real time operating system."
An indicator on the dash of your car allows you to select the speed and inside temperature desired, and a button on the dash, when pressed, places the above functions under microprocessor control. Let's
assume that you are driving down the highway and
these three functions under computer control.
the computer on.
The microprocessor
will
You press
elect to place
the button that turns
branch to a program
in its
memory
66
Basic Microprocessors and the 6800
that tells the
the
MPU
MPU to read the speed selector.
to check the actual speed;
The program
will next direct
does so by reading a sensor that generates a signal proportional to the speed. If the actual speed has not yet reached the selected speed, a signal will be generated and transmitted to an it
electromechanical device that will effectively "push on the gas."
then directs the
MPU to
The program
"read in" the temperature selected. The
MPU
will
check the actual temperature inside the automobile through another sensor. If the temperature needs to be raised or lowered, the will send a signal
MPU
to the appropriate device (either the heater or the air conditioner).
events will have occurred in alternately check the speed
much
less
The above
than a second. The program will
now
and temperature, making sure that they reach the
desired values. After the desired values are reached, the
MPU will continually
monitor them to keep both at the desired values. This is a very simplified example of a real time computer system. Now, you may ask, what about the third function? The alarm that will sound if the water temperature rises above some predetermined value? This is where the need for an interrupt arises. As we have seen, the has a separate input
MPU
The voltage on this line, in a normal V. However, when the water temperature exceeds the
data line to serve as an interrupt situation,
may be +5
predetermined
drop to zero:
line.
a sensor will cause the voltage on the interrupt line to
limit,
When
this
happens, the
MPU
executing very quickly, store the contents of so that they will be available at a later time
program
in
memory
will finish the instruction its
if
internal registers in
needed, and branch to another
that has been specifically written for situations in
the interrupt line goes low. This program
it is
memory
may sound an
which
alarm, put speed and
temperature under manual control, or perform any other function desired.
Such reactions are often described as "servicing the interrupt." The water temperature rising above limits is much more important than maintaining a constant speed or temperature. In reality, a real time computer system tions that
may
Techniques that allow the rupt
may have
cause an interrupt, even though there
is
several input func-
only one interrupt
line.
MPU to determine what function caused an inter-
when more than one function is
tied to
one interrupt
line will
be discussed
in a subsequent chapter.
5.10 Three-State Control "Three-state control"
is
a term used frequently, although often not
clearly understood. Three-state control
one device to share a
common
In Fig. 5.9, device No.
is
a technique that allows more than
bus, but not at the
same
time.
normally tied to the bus that serves as an input to the MPU. Now assume that the output status of devices Nos. 2 and 3 are needed by the MPU. If SI is opened and S2 closed, the status of device 1 is
Microcomputers—What Are They? .DEVICE
JOf
I
—o— SI
INPUT
S\
INPUT
#2
INPUT
67
DEVICE
#2
S2
DEVICE
#3
S3
V
6
BUS
#3
Fig. 5.9 Three-state control
No. 2 can be fed into the
MPU.
Likewise,
if
SI and S2 are open and S3 closed,
MPU is concerned then,
the status of S3 can be read by the MPU. As far as the each device has three states, "1", "0", and an open circuit.
By
controlling SI,
and S3, the device tied to the bus can be controlled. Fortunately, three-state gates (Fig. 5.10) are available on the market today. The device will appear as an open circuit to the bus when the three-state input is low ("0")- However, S2,
if
the three-state input goes high ("1"), the output of that device ("1" or "0")
can then be tied to the bus. Figure 5.10 shows only one for example, could represent a piece of
equipment
line.
Device No.
1,
(such as a typewriter) that
in reality has eight output lines tied to the eight lines of the data bus. In this situation, there could
be eight identical gates for each line of device No.
which the three-state control
lines
source so that the output of
all
of each gate would
be controlled by the
would be gated
eight lines
simultaneously.
DEVICE
INPUT
J8f
S
I
I
BUS THREE-STATE CONTROL JJEVICE
INPUT
I
#2
S 2THREE-STATE CONTROL DEVICE
INPUT
#
*2
#3
SITHREE-STATE CONTROL
#3
Fig. 5.10 Three-state control (cont'd)
1,
of
same
to the data bus
Basic Microprocessors and the 6800
68
Most microprocessors on ble
on the
shortly, has a pin called the in the state.
the market today have an input pin availa-
MPU for this very purpose. The M6800, which we will be reviewing "TSC"
(Three-State Control).
When
this pin is
low state, the address bus and the read/write line are in their normal However, when a high signal is applied to this pin, the address bus and
the read/write line are floating (open).
Problems
RAM
1.
What
2.
Describe the function of the address bus.
3.
4. 5.
6. 7.
the difference between a
is
and a
ROM?
Do all address lines have to be tied to each device? Do all data lines have to be tied to each device? How many bytes in a 16-bit address bus? What What
an interrupt?
is
does "three state" mean?
MPU
an has a 16-bit address bus and it is desired to address a device that responds to the address FB76, what address lines must be tied to this device?
8. If
9.
10. 11.
When
Why
is
is
an interrupt used?
three-state capability desirable?
What MPU address lines would be tied to the have an address range from 0300 to 037F7
RAM
MPU A0 Al A2 A3
A4 A5 A6 A7 A8 A9 A10 All
A12 A13 A14 A15
RAM below for the RAM to
A0 Al
A2 A3 A4 A5 A6 S3
S2S1
Programming Concepts
In the
last chapter, it
was shown that a program
is
nothing more than
a series of instructions in memory that direct the activities of the microprocessor. Computer programs are often referred to as "software." Writing a pro-
and pencil. After the program has been written, as was discussed in the last chapter. it can then be manufactured on a The ROM that contains the program may be referred to as "firmware." Once the program has been "burned" into a ROM, it is very difficult to alter. Think as you would of a "punched" card. Once the holes have been of a punched in a card, it is very difficult to alter the contents without making a
gram
requires only a paper
ROM
ROM
new
one.
6.1
Flowcharting Before someone actually starts writing a program, it is common pracis known as a "flowchart" of the activities he wishes his
tice to generate what
program
to accomplish.
FLOWCHART: A
graphical representation illustrating the logical and decisions, in sequence, that must be per-
steps, calculations,
formed to accomplish a specific
The flowchart
in Fig. 6.
1
task.
illustrates the steps
and decisions taken by
Notice the arrows indicating the direction taken after each instruction or decision block. The basic symbols the computer model described in Chap.
5.
used in writing flowcharts are shown in Fig. 6.2. After a flowchart has been generated, writing the program simple.
However, you
will
have to prove
69
this fact to yourself.
is
relatively
70
Basic Microprocessors and the 6800
PUT A NUMBER FROM INPUT BASKET INTO YOUR LEFT POCKET
PUT A NUMBER FROM INPUT BASKET INTO YOUR RIGHT POCKET
ADO THE TWO NUMBERS AND PLACE SUM IN LEFT POCKET
WRITE NUMBER ON
BLACKBOARD
C
CONTINUE
J
Fig. 6.1 Flowchart
71
Programming Concepts
PROCESS OR ACTION
DECISION
INPUT OR
OUTPUT
C
)
CONTINUE OR END OF PRESENT FUNCTION
CONNECTORS BETWEEN PAGES OF FLOW CHART
o
FLOW LINES Fig. 6.2
6.2
Assembler conversion
Mnemonics As we have stressed throughout this book,
all digital
computers oper-
ate with binary numbers only. They do not understand statements in English or any other type of language. However, most manufacturers of microprocessors do define a two-, three-, or four-letter code that describes the function of
each instruction. This code, known as a "mnemonic," has an equivalent hex (or binary)
number
to represent the function. In the computer
was
"add the
model devel-
A accumulator to the
oped in Chap. 5, one of the instructions B accumulator and place the result in the A accumulator." If you are writing even a simple program, and each instruction requires that much definition, the program would take forever to prepare. Thus, the manufacturer may assign a mnemonic code to describe such instructions. The mnemonic in this case is ABA (add A to B). Again, keep in mind that this mnemonic is only an aid to the programmer. The ABA operation may be represented by the hex code memory as 0001 101 1. Thus, when the MPU IB, which appears in the decodes the instruction, it says, "I must add the A and B accumulators together, place the result in the A accumulator, and then go to the next to
ROM
sequential location in
MNEMONIC: A
memory
for
my
next instruction."
simple code, usually alphabetic, that
sentative of the function of the instruction
it
is
represents.
repre-
72
6.3
Basic Microprocessors and the 6800
Assemblers
The question you may now have is, "How do I go from the mnemonic coding to the binary language the computer knows?" Programs written with mnemonic codes are called "source programs." It is from these source programs that the binary code
is
generated.
MACHINE LANGUAGE: and
(1 's
0's),
which
is
Another term
language computer recog-
for the binary
the only language a
digital
nizes.
Once the source code has been written to perform a task, converting machine language can be accomplished in two ways. One is to refer to the manufacturer's programming manual and manually look up the machine language equivalent for each mnemonic code in the source listing. This can be rather tedious, since calculating the branches (going to an instruction other than the next sequential one) is time-consuming and requires calculations of a very high accuracy. This manual technique, referred to as "hand assembling," is very often used by the hobbyist today but is not suitable for profesto
sional applications.
The second method of converting from mnemonic code language
is
with an "assembler."
An
assembler
is
designed to convert a source program (made up of
to machine an independent program
mnemonic codes)
into a
machine language program (see Fig. 6.3). Each type of microprocessor available on the market today must have an assembler specifically tailored for its MPU, since its hardware architecture and mnemonic codes will be different. Assemblers for different microprocessors, however, are often able to run on the same system. The assembler to convert M6800 source language to machine language can be run on an IBM 360 computer. The IBM 360 can also run an assembler written by language.
(A more
sented in Chap.
Company
X to convert
its
detailed discussion of the
source programs to machine
M6800
assembler will be pre-
8.)
SOURCE
PROGRAM (ABA TYPE INSTRUCTIONS)
COMPUTER WITH AN ASSEMBLER TO CONVERT SOURCE PROGRAM TO MACHINE LANGUAGE
Fig. 6.3 ASCII
MACHINE LANGUAGE
OUTPUT (000I ION) (ON TAPE, CARDS, OISK,
TYPEWRITER)
codes
6.4 ASCII
A term you will certainly run across sooner or later is "ASCII," which stands for American Standard Code for Tnformation interchange. This
Programming Concepts is
73
a standard code used for the interchange of information, both input and
output, to or from such devices as typewriters
6-4 that the
and
line printers.
ASCII code for an "A" is "1000001." This means
the typewriter that
is
tied to
Notice in Fig.
if you wish your system to type an "A," you must transmit
that
the signal "1000001" on the data lines to the typewriter.
Character
ASCII Code
Character
ASCII Code
@
1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 1010010 1010011 1010100 1010101 1010110 1010111 1011000 1011001 1011010 1011011 1011100 1011101 1011110 0000000 0001001 0001010 0001011
FORM FEED CARRIAGE RETURN
0001100 0001101
A B
C D E F
G H 1
J
K L
M N
O P
Q R S T U V
w X
Y z [
\ ] T
NULL HORIZ TAB LINE FEED VERT TAB
RUBOUT
1111111
SPACE
0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111
l
"
# $
% & '
( )
*
+ f
— /
1
2 3 4 5
6 7
8 9
J
<
= > ?
Fig. 6.4 ASCII Codes(7-bit)
Problems 1.
What
is
a flowchart?
Basic Microprocessors and the 6800
74 2.
Draw a flowchart of the logical steps involved in making the Easy Pound Cake described below: Ingredients
6
eggs, beaten
cups powdered sugar
4 4
cups soft butter cups flour
Vi
cup pineapple juice
1
teaspoon vanilla flavoring
1
Vi
Combine eggs and
sugar; beat in butter.
Add
flour to mixture; beat well.
Add
pineapple juice; mix well. Stir in vanilla flavoring. Place in cold oven; turn heat to 325 degrees. 3.
Bake
for
1
hour and 15 minutes.
Describe the difference between machine language program, source language
program, and assembler program.
Addressing Modes In Chap.
an oversimplified computer model was developed to illusa microcomputer system. Recall that instructions are executed in sequence, one by one, unless told to branch to some instruction at a different location in memory. As instructions are executed, they often require 5,
trate the basics of
data. This data
is usually found somewhere in memory, but immediately following the instruction.
All
memory
M6800
it
may
be found
we shall be may guess, each instruction wide and occupies one memory location.
locations in the
system, the system
studying, are eight binary digits wide. Thus, as one in the
M6800
system
eight bits
is
However, even though each instruction is eight bits, or one requires use of the next one or two memory locations.
BIT:
One
BYTE: A
byte, wide,
it
often
binary digit (thus eight binary digits comprise eight bits) unit
composed
of eight binary digits (eight bits)
an instruction requires the use of the next memory location, it is For example, assume that the number 10011101 immediately following the load A accumulator instruction is to be If
referred to as a two-byte instruction.
loaded into the
A
ROM memory, would appear as MPU has executed the instruction at location
accumulator. In the
illustrated in Fig. 7.1. After the
8000, assuming that
a one-byte instruction,
it
it is
it
will execute the instruction
at location 8001.
ADDRESSES: Common term for memory locations. Memory loca8001 would be referred to as "address 8001." Note: All addresses in this chapter will be in hex unless otherwise specified.
tion
Of binary.
course, don't forget that the instruction at address 8001
When
to take the
the
MPU
number
decodes this instruction,
will interpret
it
located in the next location (8002) and place
it
accumulator, after which
I
am to go to address 75
it
8003 for
in
is
as "I
am
in the
A
my next instruction."
Basic Microprocessors and the 6800
76
ROM CONTENTS
ADDRESS 8000
A
accumulator with number from location 8002
8001
Load
8002
10011101
8003
Fig. 7.1
Now, you may 8002
for
ask,
how
did the
next instruction?
its
ROM
address
MPU know to go to address 8003 rather than the MPU decoded the instruction at
When
address 8001, part of the information found there told it to go to 8003. An instruction may require the next two memory locations (bytes) for execution of the instruction. For example, the next two bytes may contain the address where the data can be found. If the number 1 1 1001 1 1 is to be placed accumulator but is located at address (memory location) 9150, it in the
A
ROM as shown in Fig. 7.2. The MPU would decode the instruction at address 8001 to say, "I am
might appear to take the
in
number
accumulator,
located at address 9150 and put that
after which I am to go to address
8004 for
my
number
in the
A
next instruction."
ROM CONTENTS
ADDRESS 8000 8001
Load the A accumulator with the number found at the address specified by the next two bytes
8002
91
8003
50
8004
9150
1110
Fig. 7.2
ROM
111
address (cont'd)
Addressing Modes
As you can
shown
see, the instruction
though the instruction
itself
77
in Fig. 7.2 is a 3-byte instruction, even
only requires one byte in memory.
Both examples just discussed accomplish the same end result, that is, A accumulator. Yet each found the data in a different area. Each operated in a different "mode" to accomplish the same end result. In this chapter, each of the "addressing modes" of the M6800 will be illustrated. load data into the
Many
may
instructions
operate in one, two, three, or four different modes to
accomplish the same end
result.
The M6800 has seven addressing modes: 1.
Inherent (or Implied)
2.
Accumulator Immediate
3.
4.
Direct
5.
6.
Extended Indexed
7.
Relative
Each of
7.1
these
MPU
modes
will
be illustrated with examples.
Registers
Before discussing the addressing modes of the M6800,
MPU.
the internal registers and accumulators available in the
discussed in
much
let
us review
These
greater detail in Chap. 9, but a familiarity with
needed to understand the addressing modes employed
will
be
them
is
in this chapter.
A and B Accumulator Accumulator: Often referred cumulator or
The and used
A
register
means
to
as a "register." Thus,
the
same
A
ac-
thing.
A and B accumulators are eight-bit registers located in the MPU
for data manipulation,
temporary storage locations for the
other logic functions performed by the
MPU, and
MPU.
Index Register (IR) The index to
register contains 16 bits
(two bytes).
It is
used primarily
modify addresses.
Program Counter (PC) The program counter
is
a 16-bit (two-byte) register that contains the
address of the next byte to be fetched from memory.
program
control.
It is
used to maintain
Basic Microprocessors and the 6800
78
Stack Pointer (SP) The
stack pointer
is
a 16-bit (two-byte) register that contains an
address where the status of the
MPU
may be
registers
stored under certain
conditions.
Condition Code Register (CC) The condition code
register
is
an eight-bit register used to
test
the
results of certain instructions.
7.2 Inherent (or Implied)
Addressing Mode
In the inherent addressing mode, the instruction does not require an
may also be example of an implied instruction is the "INX" instruction. This instruction says "add one to the index register." After execution of this instruction, the 16-bit index register will have been address in memory. These are always one-byte instructions. They referred to as "inherent instructions."
An
increased by one.
Accumulator Addressing Mode
7.3
Instructions in the accumulator addressing tions that address either accumulator
mode
are 1-byte instruc-
A or accumulator B. An example is the
COM A (COMplement the Accumulator) instruction. After execution of the COM A instruction, each of the eight bits in the A register will have been inverted, that
is, all
l's
become
0's
and
all 0's
7.4
Immediate Addressing Mode
data
is
become
l's.
In the immediate addressing mode, already mentioned, the "actual"
found
in the next
one or two locations immediately following the
instruction.
An number as hex
B
FO
C6
example would be an instruction The instruction to do
(11110000).
number
instruction
200, the
this will
B
register with the
be coded in
memory
(11000110). Notice in Fig. 7.3 that whatever was originally in the
register will be lost since the
the
to load a
FO
is
C6
is
located at address
(1
number
FO
replaces
it.
Also notice that after
B register, the MPU knows that its next 202. When it decoded the contents of location
loaded into the
10001 10) code told the
MPU
to
go to location 202 for
instruction. This could also be a 3-byte instruction. If a
into the stack pointer or index register,
stack pointer and the index register are
number
it requires two bytes two bytes wide.
is
its
next
to be loaded
since both the
Addressing Modes
79
BEFORE EXECUTION OF LOAD B REGISTER (C6) IMMEDIA TE
ROM ADDRESS
CONTENTS
200
08
B REGISTER
MPU READY TO 201
EXECUTE THIS
00
INSTRUCTION
F0
202
AFTER EXECUTION OF LOAD B REGISTER (C6) IMMEDIA TE
ROM ADDRESS
CONTENTS *""*"
200
C6
201
F0
B REGISTER
"*
F0
MPU READY TO EXECUTE THIS
202
INSTRUCTION
_,_,
Fig. 7.3
7.5 Direct
Immediate addressing
mode
Addressing Mode
In the direct addressing mode, the address where the data can be is in the next memory location. This is a two-byte
found (the "target address")
To illustrate, the number FO, which is stored in location 78 of Fig. be loaded in the B register. This instruction will be coded in memory as D6, or 11010110. Again, notice that the information that was in the B register has been instruction. 7.4, will
when the MPU interprets number 11010110 (D6), it directs
Also, just as in the immediate mode,
lost.
instruction represented by the binary
the the
MPU to go to location 203 for its next instruction after executing the instruction at location 201. Also notice that executing this instruction does not destroy the data (FO) at address 78. It should be emphasized that the address of the data must be specified in one byte (eight bits). Therefore, in the direct
mode, the lowest target address
7.6
is
00000000, and the highest
is 1 1
1 1 1 1 1 1
(FF).
Extended Addressing Mode The This
direct
mode
requires that addresses be specified in eight bits (one
some addresses may require two bytes. In such cases, the extended addressing mode is used. The extended addressing mode is very similar to the direct mode except that it uses three bytes of byte).
is
often not possible because
1
Basic Microprocessors and the 6800
80
BEFORE EXECUTION OF LOAD B REGISTER (D6) DIRECT
ROM ADDRESS
CONTENTS
B REGISTER
78
F0
00
200 201
D6
202
78
MPU READY TO EXECUTE THIS
«
INSTRUCTION 203
AFTER EXECUTION OF LOAD B REGISTER
(D6)
DIRECT
ROM ADDRESS
CONTENTS
B REGISTER
78
F0
F0
200 201
D6
202
78
MPU READY TO EXECUTE THIS
203
INSTRUCTION
Fig. 7.4 Direct addressing
memory
instead of two, one for the instruction
address.
To B register. The code
into the
illustrate, the
number
The
and the next two
FO located at location 905
for this instruction
Fig. 7.5 that the data address in this
following the instruction.
mode
first
mode
is
is
16
for the target
is
to be loaded
F6 (11110110). Notice
specified in the
in
two bytes
of these bytes contains the most significant
half of the address (90 16 ) and the second, the least significant half (51 16 ). decodes instruction F6 (11110110), it knows Again, after the
MPU
next instruction, upon completion of loading the data from location 9051 into the B register, will be found at address 203. Also notice that the data
that
its
in location
9051
is
not destroyed.
Addressing Modes
81
BEFORE EXECUTION OF LOAD B REGISTER (F6) EXTENDED
ROM ADDRESS
CONTENTS
200
B REGISTER
MPU READY TO
201
EXECUTE THIS
F6
00
INSTRUCTION 202
90
203
51
204
9051
F0
AFTER EXECUTION OF LOAD B REGISTER
(F6)
EXTENDED
ROM ADDRESS
CONTENTS
B REGISTER
200
F6
F0
201
90
202
51
MPU READY TO EXECUTE THIS
203
INSTRUCTION
9051
F0
Fig. 7.5
7.7
Indexed
Mode
Extended addressing more
of Addressing
The indexed mode of addressing
uses a 2-byte instruction.
The next
from the instruction contains a number (often referred to as an "offset") that is added to the contents of the index register to form an address. This new address, as in the extended mode, contains the data. As an example (Fig. 7.6), assume that the index register contains the number 5430 (in hex). It is desired to put the data found in location 5453, FO, in the B register. The instruction to load the A register from the address that is formed by adding location
82
Basic Microprocessors and the 6800
the contents of the next location to the contents of the index register
E6
is
hex
The next memory location contains the number 23 (in hex) 5430 when added to 23 forms the address 5453. Recall that since the
(11100110).
since
index register
The
is
16 bits long, a 16-bit address can be generated.
MPU decodes the instruction just as before- and knows
it is
to get
would appear that this mode of generating an address is the same as the extended mode, but such is not the case. Since the index register can be incremented or decremented by 1, data its
next instruction at location 202.
At
first, it
BEFORE EXECUTION OF LOAD B REGISTER
(E6)
INDEXED
ROM ADDRESS
CONTENTS
B REGISTER
MPU READY TO EXECUTE THIS
E6
200
00
INSTRUCTION 23
201
INDEX REGISTER
202
5430
5453
F0
AFTER EXECUTION OF LOAD B REGISTER
(E6)
INDEXED
ROM ADDRESS
CONTENTS
200
E6
201
23
202
B REGISTER *
F0
MPU READY TO FYPPl ITF THI^
,
INDEX REGISTER
INSTRUCTION 5430
5430
F0
'Remember that the effective address
is
formed by adding the contents of the index register address equals 5430
to the contents of the next byte after the instruction. In this case, the
plus 23, or 5453. Fig. 7.6 Index addressing
mode
Addressing Modes
83
can be stored in consecutive memory locations by incrementing or decrementing that register. This feature will be used in sample programs later on. Additionally, the index mode requires only one byte after the instruction
whereas the extended mode requires two.
7.8 Relative In this
Addressing Mode
mode of addressing,
the next instruction to be executed by the
MPU is located at some other address than the one following.
These
will
be
MPU
categorized as "branch" instructions. Such instructions cause the to go to some other address for its next instruction in accordance with some condition within the "condition code" register. These conditions will be studied as
each instruction is reviewed in a later chapter. For now, only the mechanics of calculating where the is to get its next instruction will be shown.
MPU
Branch instructions are two bytes long. The next location following the branch instruction tells the MPU where it is to get its next instruction, providing certain conditions are met. Since the
both forward and backward, each operation
MPU
will
is capable of branching be reviewed separately.
Branching Forward from Present Location As mentioned above, the next location after the branch instruction contains the information telling the how it is to branch for its next instruction. When the interprets an instruction as a branch instruction,
MPU
MPU
it
will
decode
it
as a two-byte instruction. If
it
didn't branch to a different
would next execute the instruction at its present location plus two. Therefore, the branch must be referenced from its present location plus two. location,
it
Consequently, the
MPU will take the contents of the memory location immedi-
ately following the
two.
The
branch instruction and add it to the present location plus is the address where the MPU is to get its next
result of this addition
instruction.
The
MPU will then continue executing instructions from this new
location.
To
illustrate
struction, at
memory
with an example, assume that the "branch always" inlocation 0200, is to be executed (Fig. 7.7). It is desired
branch forward to location 0225. The hex code for the "branch always" is 20, which will be at location 0200. The number located at memory location 0201 will be hex 23. Therefore, the address for the next instruction will be at location 0225 (present location of 200 + 2 + 23). There is a maximum number of forward memory locations which can be branched over since there is only one byte which can be used for this purpose. The leftmost bit must be kept as a "0" since it is this bit that tells to
instruction
MPU
the "1," the
to
branch forward. Therefore,
maximum number
if all the remaining seven bits are a of locations that can be branched forward is
1111111, or 7F, or 127 10 locations.
Basic Microprocessors and the 6800
84
BEFORE EXECUTION OF BRANCH ALWA YS (20) INSTRUCTION (FORWARD)
ROM CONTENTS
ADDRESS 200
MPU WILL
200
20
201
23
FXECUTE THIS
<
INSTRUCTION NEXT 202
225
AFTER EXECUTION OF BRANCH ALWAYS (FORWARD)
(20)
INSTRUCTION
ROM ADDRESS
CONTENTS
200
20
201
23
MPU WILL EXECUTE THIS
<
225
INSTRUCTION NEXT *.^^.-»
-«.-«.
Fig. 7.7 Relative addressing
mode
(branch forward)
Branching Back from Present Location The
MPU is capable of branching back from its present location just
can branch forward. Again, the branch is referenced from its present location plus 2. The number immediately following the branch instruc-
as easily as
it
tion, just as before, tells the
MPU how far
it is
to branch.
However, the number
must be expressed in 2's complement. For example, assume that we are to branch to memory location 0195 from our present location, 0200. The calculations for the offset are as follows:
Present location
+
2
Final location
= =
0202 (hex) 0195 (hex)
6D
(hex)
Addressing Modes
(You may wish
85
to verify this subtraction in binary
if
the subtraction in hex
is
confusing.)
6D(hex) l's
2's
complement complement
= = =
01101101 10010010 10010011 This "1"
tells
the branch
Therefore, the
number immediately following
would be 10010011, or 93 16 The next instruction location 0195 (Fig. 7.8). .
is
the
MPU
backwards
the branch instruction
to be executed will be at
BEFORE EXECUTION OF BRANCH ALWA YS (20) INSTRUCTION (REVERSE)
ROM ADDRESS
CONTENTS
0195
MPU WILL 200
20
201
FYPfMITF
,
THI*^
INSTRUCTION NEXT
93
202 ^^
AFTER EXECUTION OF BRANCH ALWA YS
(20)
INSTRUCTION
(REVERSE)
ROM ADDRESS
CONTENTS
MPU WILL EXECUTE THIS INSTRUCTION NEXT
0195
200
20
201
93
202 .^
J
Fig. 7.8 Relative addressing
mode
(branch back)
86
Basic
7.9
M icroprocessors and the 6800
Summary The instruction
"Load the B
to
register"
in four differ-
indexed. Notice that the hex code
and The whole exercise simply means this: If, while your program, the actual data is in the next one or two bytes, then use
ent modes: immediate, direct, extended, for each
writing
was described
mode was
different.
the instruction code for the immediate mode. If the data
is
located at an
address that is one byte wide, then use the instruction code for the direct mode. If the data is found at an address that requires two bytes to specify, then use the instruction code for the extended mode. If the data
is
at
an address which
is specified by adding the next byte to the index register to form a new address, then use the instruction code for the indexed mode. The branch instructions are self-explanatory. As can be seen in Fig. 7.9, the codes for the "Load B
Register" instruction are quite different.
Mode
LOAD LOAD LOAD LOAD
Instruction
B IMMEDIATE B DIRECT B EXTENDED B INDEXED Load B
Fig. 7.9
code
C6 D6 F6 E6
register addressing
modes
Problems 1.
2.
What What
addressing is
mode
is
used for
all
branches?
the difference between the immediate addressing
mode and
the direct
addressing mode? 3.
If
it is
will
desired to load the
be addressed
if
the index register contains the hex
next byte from the load 4.
How many
A accumulator in the indexed mode, what location
locations
A
is it
number 4201 and the
instruction contain a 10?
possible to branch over in the forward
and reverse
direction?
a branch always instruction were located at address 4050 and it was desired to branch to address 4080, what would the contents of 4051 be?
5. If
problem 5, it was desired to branch to address 4000, what would the contents of 4051 be? What is the difference between the direct mode and extended mode of address-
6. If in
7.
ing? 8.
Calculate the destination address for the following branch instructions:
Addressing Modes
x Address
Hex
Contents
4014 4015
20
5535 5536
20
F8
14
800F
20
8010
E6
99AB 99AC
20
F2
87 Destination Address 1
8
M6800 Software Chap. 7, a single instruction may have one, two, modes. Yet although there may be up to four modes for a single instruction, the end result of an instruction is the same. Each where to find addressing mode is just a different manner of telling the
As we observed
in
three, or four different addressing
MPU
the data.
The M6800 instruction set includes 72 separate instructions; however, more than one addressing mode, there are 197 valid machine codes. For example, the ADD A instruction has an 8B operation code for the immediate mode, 9B operation code for the direct mode, BB since each instruction can have
operation code for the extended mode, and an
AB
indexed mode. In the immediate mode, the data
in the next byte of memory,
yet in the other three
modes the data
is at
is
operation code for the
some other memory
In this chapter, each instruction of the
M6800
address.
be reviewed. All
will
addressing modes for each instruction will be summarized, and the hex operation code for each addressing
mode
listed.
Many
to illustrate the contents of applicable registers
examples
before and
will
be presented
after execution of
an instruction. A sample source listing is also shown for all 72 instructions in each mode. When a sign is shown, the instruction is in the immediate mode, sign is located in the next byte of memory. number and the following the When a $ sign is shown, it indicates that the next number is in hex. If a sign is not present, then the number following the $ is a hex address in memory. The indexed addressing mode is shown with a hex number, followed by a comma, and an X ($10,X). The number following the $ sign is added to the contents of the index register to form a new effective address. For example,
#
#
#
1.
LDA A #$25
indicates that the data of 25
is
in
hex (immediate
mode). 3.
LDA A LDA A
$25 indicates that hex 25 is an address (direct mode). $2525 indicates that hex 2525 is an address (extended
4.
LDA A
$25,X indicates that the address
2.
mode).
25 to the contents of the index register to form a
88
is
formed by adding hex
new address (indexed mode).
M6800 Software
89
The M6800 microprocessor has a "condition code
register" that has
certain bits set or cleared in accordance with the results of certain instructions.
The
eight bits of the condition code register are as follows:
C V
(carry-borrow)
Bit 1:
Bit 2:
z
(zero indicator)
Bit 3:
N
(negative indicator)
Bit 4:
I
(interrupt
Bit 5:
H
(half-carry)
Bit 0:
Bits
6 and
7:
(2's
complement overflow
indicator)
mask)
Always "1"
Included in the description of each instruction
is
a
of the
listing
condition code register bits affected. If the letter of the condition code register bit is
shown, refer to Fig.
8. 1
for the explanation of that letter.
Should any of
these explanations be inapplicable for a particular instruction, the correct
explanation will be given at the end of the instruction.
H:
Set
I:
Cleared.
there
if
was a
carry from
N:
Set
if
the most significant
Z:
Set
if
all bits
V:
Set
if
there
bit
bit 3;
cleared otherwise.
of the result is set; cleared otherwise.
of the result are cleared; cleared otherwise.
was a
two's complement overflow as a result of the operation; cleared
otherwise. C:
Set
there
if
was a
carry from the
most
significant bit of the result; cleared otherwise.
Fig. 8.1 Condition
8.1
M6800
code
register
Instruction Set
This section contains the complete instruction
set for the
M6800 mem-
microprocessor. All addresses and examples used, including .register and
ory contents, have been randomly selected and are shown for illustrative
purposes only. Parentheses are used to indicate "contents of." For example,
(A accumulator) means "the contents of the A accumulator." shown in many examples to indicate the next instruction that will be executed by the MPU. The three letters in quotation marks at the beginning
the expression
An
arrow
is
of each instruction comprise the
mnemonic
for that instruction.
Add Accumulator B to Accumulator A The contents of the A accumulator are added to the contents of the B accumulator, the sum going into the A accumulator. The B accumulator is "ABA ":
not changed.
90
Basic Microprocessors and the 6800
Execution
Time
(Cycles)
Instruction
Source Listing
Code (Hex)
Example
IB
ABA
2
The condition code
C
register bits affected are as follows:
H, N, Z, V,
(see Fig. 8.1).
BEFORE EXECUTION OF ABA INSTRUCTION
MEMORY ADDRESS
CONTENTS
A ACCUMULATOR
B ACCUMULATOR
200
1B
10000001
00011000
201
AFTER EXECUTION OF ABA INSTRUCTION
200
A ACCUMULATOR
B ACCUMULATOR
10011001
00011000
1B
201
"ADC":
Add
with Carry
The contents of the
C bit
in the condition
code register are added to
A accumulator or the B accumulator and a memory being placed in that same A or B accumulator.
the contents of either the location, the result
Execution
Mode
A IMMEDIATE A DIRECT A EXTENDED
Time
(Cycle) 2
Instruction
Code (Hex) 89
3
99
4
B9
5
A9
Source Listing
Example
ADC A ADC A ADC A
#$25 $25
$7168
Explanation
Note 1 Note 2 Note 3 (see
A INDEXED B IMMEDIATE B DIRECT B EXTENDED B INDEXED
2
C9
3
D9
4
F9 E9
5
The condition code
C
(see Fig. 8.1).
ADC ADC ADC ADC ADC
A
$25,X
B B B B
#$CE $AD $CCCC $D2,X
Note Note Note Note Note
register bits affected are as follows:
example)
4 5
6 7 8
H, N, Z, V,
M6800 Software
91
NOTES: 1.
(C)
-|-
2.
(C)
-|-
+ 4. (C) + 3.
(C)
(A accumulator) + hex 25 \ (A accumulator) + (hex address 25) I (A accumulator) + (hex address 7168) \ (A accumulator) + (address specified 1 by index
5.
(C)
-|-
6.
(C)
7.
(C)
+ +
register
+
+
(C)
+
+
(B accumulator)
by index
I
(hex address
f
accumulator
Ke
+
hex D2)
ult ls piaced
L
ln
u
(address specified 1
register
placed
is
A
\
AD)
CCCC) / 8.
in
hex 25) /
(B accumulator) + hex 25 (B accumulator) + (hex address
(B accumulator)
Result
or
I
BEFORE EXECUTION OF ADC INSTRUCTION (EXAMPLE USING A EXTENDED MODE—ADC A $7168)
MEMORY ADDRESS
CONTENTS
A ACCUMULATOR
200
B9
01100000
201
71
202
68
CONDITION CODE REGISTER
C
203
7168
1
00010010
W OF ADC INSTRUCTION
AFTEI? EXECUTIC
MEMORY ADDRESS
CONTENTS
A ACCUMULATOR
200
B9
01110011
201
71
202
68
CONDITION CODE REGISTER 203
7168
00010010
C
Basic Microprocessors and the 6800
92
"ADD":
Add
Without Carry
A accumulator or the B accumulator are added
The contents of the to the contents of a
memory
location, the
sum going into that same accumula-
tor.
Execution
Mode
Time
A IMMEDIATE A DIRECT A EXTENDED
Example
3
8B 9B
4
BB
ADD A #$DA ADD A $DA ADD A $DA53 ADD A $DA,X ADD B #$21
Note Note Note Note Note
ADD B $4D ADD B $ADFF ADD B $55,X
Note 14 Note 15 Note 16
2
A INDEXED B IMMEDIATE
Source Listing
Instruction
Code (Hex)
(Cycles)
2
AB CB
3
DB
5
Explanation 9 10 11
12 13
(see
B DIRECT B EXTENDED B INDEXED
The
C
FB EB
4 5
example)
condition code register bits affected are as follows: H, N, Z, V,
(see Fig. 8.1).
NOTES: 9.
10. 11. 12.
(A (A (A (A
DA
+ +
hex
accumulator)
(hex address
DA)
Result to
accumulator)
-f
(hex address
DA53)
accumulator
accumulator)
accumulator)
+
(address specified by'
index register
+
hex DA),
hex 21
13.
(B accumulator)
-f
14.
(B accumulator) (B accumulator) (B accumulator)
+ (hex address 4D) + (hex address ADFF) + (address specified by index register + hex 55)
15. 16.
A
Result to
B
accumulator
BEFORE EXECUTION OF ADD INSTRUCTION (EXAMPLE USING ADD B #21)
MEMORY ADDRESS
CONTENTS
200
CB
201
00100001
202
B
ACCUMULATOR 00001110
93
M6800 Software
AFTER EXECUTION OF ADD INSTRUCTION B ACCUMULATOR 00101111
200
CB
201
00100001
202
"AND":
Logical
Each
bit
AND
of the
corresponding bit of a
A or B accumulator is logically "ANDed" with each
memory
location, the result going into that
same
ac-
cumulator. Execution
Mode
Time
A IMMEDIATE A DIRECT A EXTENDED A INDEXED B B B B
IMMEDIATE DIRECT EXTENDED INDEXED
(Cycles)
Instruction
Source Listing
Code (Hex)
Example
2
84
3
94
4
B4
5
A4
2
C4
3
D4
4
F4 E4
5
Explanation
AND A #$C2 AND A $6F AND A S3DCA AND A $F1,X •
ANDB
#$10
AND B AND B AND B
$10
$1000
$10,X
Note Note Note Note Note Note Note Note
17 18 19
20 21
22 23
24
(see example)
The condition code 8.1);
V
will
register bits affected are as follows:
N,
Z (see
be cleared.
NOTES: 17. 18.
(A accumulator) "ANDed" with hex C2 | (A accumulator) "ANDed" with (hex ad- I dress 6F) I Result in with (hex ad- / accumulator dress 3DCA) I
A
19.
(A accumulator) "ANDed"
20.
(A accumulator) "ANDed" with specified
by
(B accumulator) 22. (B accumulator) 21.
index register
+
(address I
hex Fl)
J
\ "ANDed" with hex 10 "ANDed" with (hex ad- I dress 10)
"ANDed"
with (hex ad-
I Result in B V accumu iator
23.
(B accumulator)
24.
(B accumulator) "ANDed" with (address 1 specified by index register + hex 10) 1
dress 1000)
/
Fig.
1
94
1
Basic Microprocessors and the 6800
BEFORE EXECUTION OF AND INSTRUCTION (EXAMPLE USING AND B $10,X)
MEMORY ADDRESS
CONTENTS
INDEX REGISTER
"-
200
E4
201
00010000
0000 0011 0010 0000
202
B
ACCUMULATOR
rxxrjr 00011001
330
00111111
AFTER EXECUTION OF AND INSTRUCTION
MEMORY ADDRESS
CONTENTS
INDEX REGISTER
200
E4
0000 0011 0010 0000
201
00010000
202
B
ACCUMULATOR 00011001
330
001
1 1 1 1
formed by adding the contents of the index in the program (0320 + 10 = 0330). At hex address 330 is the number (001 11111), which is to be "ANDed" with the contents of the B accumulator (00011001) to produce the result 00011001. Notice that the address
register to the
"ASL":
Arithmetic Shift Left
All bits of the
A accumulator, B accumulator,
are shifted one place to the
the
"C"
bit
is
hex number specified
left
with the most significant
of the condition code register.
or a
>-
t BIT 7
location
loaded into
A zero will be loaded into the least
significant bit (bit 0) of the location being shifted.
~-C
memory
bit (bit 7)
BIT0
•
95
M6800 Software Execution
Mode
Time
(Cycles)
Source Listing
Instruction
Example
Code (Hex)
Explanation
48
ASL A
2
58
ASLB
6
78
ASL S67AD
Note 25 Note 26 Note 27
7
68
ASL
Note 28
A ACCUMULATOR B ACCUMULATOR
2
EXTENDED ADDRESS INDEXED ADDRESS
(see example)
The
condition code register bits affected are as follows:
N,Z
See Fig.
V
Set
Set
8.1.
completion of the
after the
if,
"1" and
C
$25,X
(N
shift operation, either
is
C is "0") or (N is "0" and C is "1"); cleared otherwise.
before the operation, the most significant bit of the
if,
location being shifted
was
set;
cleared otherwise.
NOTES: (A accumulator) shifted left one place (B accumulator) shifted left one place 27. (Hex address 67 AD) shifted left one place 28. (Address specified by index register + hex 25.
26.
25) shifted
left
(Bit 7)
"0"
is
loaded
is
into the
C
bit;
loaded
into bit
one place.
EXECUTION OF ASL INSTRUCTION (EXAMPLE USING ASL $67AD)
BEFORE EXECUTION
AFTER EXECUTION
MEMORY
MEMORY
ADDRESS
CONTENTS
200
78
201
67
201
67
202
AD
202
AD
203
ADDRESS *
CONTENTS
200
78
203
~*
67AD
11111111
67AD
J
11111110
jrrrr CONDITION CODE
F
EGISTER
C
CONDITION CODE REGISTER
C 1
a
Basic Microprocessors and the 6800
96
Notice that that a "0"
is
'ASR ».
bit 7
of hex address 67
AD is shifted into the C bit and
of hex address 67 AD.
loaded into bit
Arithmetic Shift Right
All bits of the
A accumulator, B accumulator,
are shifted one place to the right. Bit
The
condition code register.
will
contents of bit 7 will not
r?
h~
C
address
of the
bit
be changed.
a
BITO
BIT 7
Execution
Mode
memory
or a
be loaded into the
Time
Instruction
(Cycles)
Code (Hex)
Source Listing
Example
Explanation
A ACCUMULATOR
2
47
ASR A
Note 29
B ACCUMULATOR
2
57
ASRB
EXTENDED ADDRESS INDEXED ADDRESS
6
77
7
67
ASR $ABF1 ASR S14.X
Note 30 Note 31 Note 32
(see
The condition code
N,Z
See Fig.
V
Set
if
C
Set
if,
register bits affected are as follows:
8.1.
after the
completion of the
C is "0") or (N is "0"
"1" or
example)
and
shift operation, either
(N
is
C is "1"); cleared otherwise.
before the operation, the least significant bit of the loca-
tion being shifted
was
set;
cleared otherwise.
NOTES: 29. 30.
31. 32.
\ shifted right one place I (B accumulator) shifted right one place (Hex address ABF1) shifted right one place > (Address specified by index register -f hex 1 14) shifted right one place/
(A accumulator)
A
Bit
will
be
loaded into the
C
bit; bit
7
remains the
same
accumulator is shifted into the C bit. Also of the the same, yet the contents of bit 6 remained 7 of bit notice that the contents Notice that
bit
were changed to match
bit 7.
97
M6800 Software
EXECUTION OFASR INSTRUCTION (EXAMPLE USING ASR A) AFTER
BEFORE
MEMORY
MEMORY ADDRESS
CONTENTS
200
47
CONTENTS
ADDRESS -
47
200 201
201
A ACCUMULA1TOR
A ACCUMULATOR
10000001
11000000
CONDITION CODE REGISTER
CONDITION CODE REGISTER
C
C 1
Branch Instructions All branch instructions, except the "branch always" and the "branch to subroutine" instructions, tion code register.
depend on the status of various
bits in the condi-
The condition code register bits are set or cleared by
instruction executed
by the
MPU
before the branch instruction
is
encountered. If the conditions for the branch
are met, the next instruction executed by the
contents of the next byte plus
its
MPU
present address plus
will
be specified by the
2. If
the conditions for
the branch are not met, the next instruction executed by the
a location equal to
its
present address plus
The contents of a condition code instruction.
For example, the
the last
that affected the condition code register
BCC
MPU will be at
2.
register are not affected
("branch
if
by a branch
carry clear") instruction
tells
MPU to check the contents of the C bit in the condition code register. If the C bit is "0" (or clear), the next instruction executed by the MPU will be the
at a location equal to its present address plus 2 plus the contents of the byte
immediately following the BCC instruction. If the C bit is a "1," branching will not take place, that is, the next instruction to be executed by the will be at its present address plus 2.
MPU
The various branch instructions are listed in Table 8.1. Notice that of them are two-byte instructions. (See Sec. 8.4 for examples of conditional branches.) all
98
Basic Microprocessors and the 6800
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21
Fig. 9.5
M6800
pin outs
GROUND
via the
M6800 Microcomputer Family 1.
Ground
ground, which 2.
(Pins 1
153
These pins must be
and 21)
tied to the
system
power supply. When the input on this pin is in the high
the negative side of the 5-volt
is
HALT
(Pin 2)
state
MPU will fetch and execute instructions. When the HALT line goes processing before low, the MPU will finish execution of the instruction in the halt mode, the Bus Available (BA) line will halting. When the MPU
("1"), the
it is
is
be high, the Valid
(R/W)
Write
Memory Address (VMA)
be low, and the Read/-
line will
the address bus, and the data bus will be in the high-
line,
an interrupt (IRQ or NMI) should occur while the MPU will be latched into the MPU until the latter is taken out of the halt mode, at which time it will service the interrupt. The HALT line permits an external source to control program execution by executing one instruction at a time. This capability is particularly useful during program debugging. During normal operation of a system, this pin would be tied to
impedance is
state. If
in the halt state,
+5
it
V.
Phase 1 Clock (Pin 3) The NMOS clock will be inputted on this pin. 4. Interrupt Request Line (IRQ) (Pin 4) 3.
the
PIAs
(or
some
l
output of the system
When the IRQ line from
other external device) goes low, the
MPU will complete the
executing and then go into an interrupt sequence, providing the interrupt mask has not been previously set to inhibit interrupts. During the first step in this sequence, the contents of the index register, the program counter, the A and B accumulators, and the condition code register will be stored on the stack (in RAM) for later use. Next, the I bit in the condition code register will be set to a " 1 " so that no further interrupts may occur. The MPU will now load the contents of the highest ROM address minus 6 and the contents of the highest ROM address minus 7 into the program counter. This vectoring address will occur when the MPU puts the addresses FFF8 and FFF9 on the address bus. The contents of these locations contain the address of the program that is to service the interrupt by prescribing the action the MPU is to take because of the interrupt. At some point in the servicing program, an RTI instruction will be encountered that will cause the MPU and its internal registers to be restored to the condition they were in before the instruction
it is
interrupt. See Fig. 9.6 for a detailed flowchart of the interrupt sequence.
The IRQ sequence
is
as follows:
(1) If th e I bit in the condition
IRQ
code register
goes low for at least one
2
is
cycle, the
not
set (I
IRQ
=
0)
and the
sequence will
be entered.
completion of the current instruction, internal registers PC, X, A, B, and CC will be stored in at the address indicated by the stack pointer in descending locations (seven bytes in all).
(2) After
RAM
(3)
The IRQ mask
(4)
Data
at
FFF8
(I bit
=
1) is set.
gets loaded into
PCH.
154
Basic Microprocessors and the 6800 (5)
Data
(6)
PC
FFF9
at
PCL.
gets loaded into
contents go out on address bus during
l.
Contents of the location addressed enter instruction register during 2 and are decoded as first instruction of interrupt routine.
(7)
(8) If it is a
more than
1-byte instruction, additional bytes enter
MPU for
execution. If not, go to next step. (9) After execution, step 7
loop
The SWI sequence (1)
Contents of
is
(4)
(5) (6)
The IRQ mask Data Data
is
by the stack pointer
in
descending location
all).
(I bit
=
1) is set.
at
FFFA
gets loaded into
PCH.
at
FFFB
gets loaded into
PCL.
PC contents go out on address bus during 1. Contents of the byte addressed enter instruction register during and are decoded as first instruction of SWI subroutine.
(7) If
more than a one-byte
it is
The
executed.
MPU registers PC, X, A, B, and CC are stored in RAM
(seven by tes in (2)
"RTF'
as follows:
at the address indicated
(3)
repeated for subsequent instructions.
is
repeated until the instruction
is
instruction, additional bytes enter
2
MPU
for execution. If not, go to next step. (8) After execution, step 6 is repeated for
loop
state,
a signal from the
it is
(VMA)
MPU
subsequent instructions. The
RTI
repeated until the instruction
Valid Memory Address
5.
high
is
(Pin 5)
to
all
is
executed.
When
this line is in the
devices tied to the address bus
that there is a valid address in the address bus. This line will be either a "1" or a "0". The signal is not three-state. 6.
to the
the
Nonmaskable Interrupt (NMT)(Pin
IRQ input,
MPU
will
except that the interrupt
is
6)
This input pin
nonmaskable.
As with
complete the instruction being executed before
it
is
similar
the
IRQ,
recognizes
NMI interrupt. After the contents of the program counter, index register, and B accumulators, and the condition code register have been stored on
the
A
the stack
ROM
(RAM)
locations
for later use, the
FFFC
and
I bit
FFFD
will
be
will next
set to a "1".
The
contents of
be loaded into the program
counter. These locations contain the address of the
nonmaskable
interrupt. Again,
in the servicing
condition
it
was
program,
it,
in before the
when
the
along with
MPU
program that services the comes to an RTI instruction
its registers, will
nonmaskable
be restored to the
interrupt. See Fig. 9.6 for a detailed
flowchart of the interrupt sequence.
The
NMI
sequence
is
as follows:
NMI goes low for at least one 2 cycle, the completion of the current instruction.
(1) If the
MPU will wait for
WAIT FOR INTERRUPT (WAD
SOFTWARE INTERRUPT (SWII
HARDWARE INTERRUPT
MASK
NON fl
SET
ASKABLE^
CONTINUE MAIN PROGRAM
*o SP6
CONDITION CODE
SP5
ACCUMULATOR B ACCUMULATOR A
SP4 SP3
INDEX REGISTER (MS)
SP2
INDEX REGISTER
SP
PROGRAM COUNTER PROGRAM COUNTER
1
SP
HARDWARE HARDWARE SOFTWARE
(MS)
FFF8
(LSI
FFF9
(MS)
FFFA
SOFTWARE (LS) NON-MASKABLE
(LS)
(MS* (LS)
FFFB (MS)
NON-MASKABLE(LS)
FFFC. IFFFC^
FFFD^
|fffd|
RESTART
(MS)
FFFE
RESTART
(LS)
FFFF
LOAD INTERRUPT VECTOR INTO PROGRAM COUNTER
INTERRUPT
PROGRAM Fig. 9.6 Interrupt flow chart
(2)
The
internal registers
RAM
PC, X, A, B, and CC will then be stored in by the stack pointer in descending
at the address indicated
locations (seven bytes in (3)
The IRQ
(5)
Data Data
(6)
PC
(4)
(7)
at at
(bit
1=1)
all).
mask
is set.
FFFC is loaded into PCH. FFFD is loaded into PCL.
contents go out on address bus during
(f>l.
Contents of the location addressed enter instruction register during 4>2 and are decoded as first instruction of NMI subroutine.
(8) If
it is
a more than one-byte instruction, additional bytes enter
for execution. If not,
go to next
step.
(9) After execution, step 7 is repeated for
loop
is
MPU
repeated until the instruction
subsequent instructions. This
RTI
is
executed.
156
Basic Microprocessors and the 6800
Bus Available (BA)
7.
low
state, indicating that
control.
When
available, tha t if
this line will
MPU
bus and the data bus are they are in a high-impedance state. This condition will occur
HALT line is in the halt (low) mode or the MPU is the result of the WAI instruction.
the
as
be in the
in the high state, the address
it is is,
Normally,
(Pin 7)
the address bus and the data bus are under
in a wait condition
Power (Pin 8) This pin must be tied to the positive power supply. Address Lines (A0-A15) (Pins 9 through 20 and 22 through 25) -f 3 -Volt
8.
side of the 5-volt system 9.
These 16 output
MPU. The MPU. The outputs of the 16 lines are three-state of driving one standard TTL load and 130pF at 1 MHz.
lines are
used to address devices external to the
addresses are generated by the
bus drivers capable
When
the output
is
turned
off,
the circuit
essentially open.
is
Data Lines (D0-D7) (Pins 26 through 33)
These eight bidirecfrom the MPU and vice versa. They can be put in the three-state condition (high impedance) and have three-state output buffers capable of driving one standard TTL load and 10.
tional lines are used to transfer data to a peripheral device
BOPfat
MHz.
1
Read/Write Line (R/W)
11.
the is
high ("1") or in a Write state (send)
stand-by state state it
when
will
is
1
the high, or Read, state.
2.
OFF
in the data
The
clock.
in a
Read
state if the line
low ("0"). The normal put in the high-impedance
the line
is
line is
Data Bus Enable (DBE) (Pin 36)
(2)
it is
when
the processor
is
halted,
state (high impedance).
the data bus output drivers
phase 2
if
the three-state line goes high. Also,
be in the
This signal generated by
(Pin 34)
MPU tells all devices external to itself that
When
bus during the
when
This input signal will enable
in the high state. It is
in the high state,
it
will
normally from the
permit data to be output
MPU write cycle. During the MPU read cycle, the
data bus drivers will be disabled internally. 13. is
Phase Two Clock (Pin 37)
The
2
output of the system clock
inputted on this pin. 1
4.
Three-State Control (TSC) (Pin 39)
This high input causes
address lines and the read/write line to go into the high-impedance
state.
all
The
VMA (Valid Memory Address) and BA (Bus Available) signals will be forced low, thereby preventing a false read or write to or from a device enabled by
VMA line. The data bus
TSC and has its own enable code. and clock inputs must be held high 1 2 and low, respectively, in order to delay program execution and free the address bus for use by other devices. Since the MPU is a dynamic device, caution must the
When
the
is
not affected by
TSC line is held high,
the
be taken not to hold the system in the three-state condition for longer than 9.5 /msec or the data in the will be destroyed. 15. Reset (RES) (Pin 40) This input signal is used to start the
MPU
MPU from a power-down condition. After the power is turned on and reaches RES input must be held low for at least eight clock cycles, during which time the address bus contains the address FFFE. After a minimum of
4.75 V, the
157
M6800 Microcomputer Family
GOTO LOCATION DETERMINED BY PC AND BEGIN INITIALIZATION
Fig. 9.7 Restart
Table
9.1
M6800
Pin
Signal
Signal Description
Pin No.
sequence
Summary
Name
Signal
Three
Type
State
Ground
GND
Input
2
Halt
HALT
Input
3
Phase
*1
Input
4
Interrupt
5
Valid
6
Nonmaskable Bus Available Power
1
7
8
9-20 22-25
1
Memory Address Interrupt
)
Address Lines
Input
A0-A15
Output
Yes
IRQ
Input
VMA
Output
NMI
Input
BA
Output
J
21
Ground
26-33 34
Data Lines Read/Write Not Used Data Bus Enable
35,38
36 37 39 40
Phase 2 Three-State Control
Reset
eight clock cycles, the
RES
line
to begin the restart sequence.
FFFE
4-5
No No No No No No No No
will
may
GND
Input
No
D0-D7
Input/Output
R/W
Output
Yes Yes
DBE
Input
4>2
Input
TSC RES
Input Input
No No No No
MPU
be allowed to go high to signal the location addressed by
The contents of the
ROM
be placed in the most significant byte of the program counter, and location addressed by FFFF will be placed in its least
the contents of the
ing routine.
ROM
The program counter now contains the address of the initializDuring the restart sequence (Fig. 9.7), the interrupt mask bit (I)
significant byte.
158
Basic Microprocessors and the 6800
V)
a.
c
C
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eo en
0.3
W
-
02
u. Vqq
01 and
01,02
V)
V
0.5
°-3
V)
+
+
0.3
Separation
=
Time
1)
Vqv
Vqc
Width
(Figure
at
SS
V
Vss -
Up 02
between
Clock
Times
at
Duration
or Fall
and Time
Pulse
(Measured
(Measured
Time
(Measured
01 and
Timing
Overshoot
Cycle Clock
Total
Rise
Clock
Delay
159
M6800 Microcomputer Family of the condition code register start-up
The 1. 1
and
Part of the initialization procedure in the
is set.
program might use the CLI instruction that
2,
2.
reset sequence
While
is
resets the I bit to "0".
as follows:
HALT is high, RESET goes low for at least eight cycles of
during which time the interrupt bit
FFFE
Contents of
(I) is set.
are loaded into the
program counter (most
significant byte). 3.
Contents of FFFF are loaded into the
PCL program counter (least
significant byte). 4.
PC
Table
contents go out on address bus during 9.
1
gives a
M6800
1.
pin summary.
System Clock
As mentioned in Chap. 5, all digital systems must have a clock signal may be accomplished in a timed, orderly manner. The M6800
so that functions
Microcomputer System
is
no different.
It
requires a two-phase nonoverlapping
clock capable of operating from the 5-V system power.
shown
clock specifications are
The waveform and
in Fig. 9.8.
It will be the purpose of this section to describe the operation of the are based around system clock and to show how all operations in the
MPU
it.
MPU
Inside the
is
a register called an instruction register (IR), whose
purpose is to decode instructions so that the MPU knows which one and which of the various addressing modes is to be used.
When
the phase
1
(l)
is
current
clock signal goes high, the contents of the
program counter are transferred to the address bus. While this is taking place, VMA will go high ("1"), indicating a valid address. On the falling edge of l, the program counter will be incremented by one. When 2 goes high (assuming that the 2 clock signal is used as a chip select or an enable), data from the memory location addresses is placed on the address bus, and during
-
CONTENTS OF PROGRAM COUNTER PLACED ON ADDRESS BUS
PHASE
I
CYCLE PROGRAM COUNTER INCREMENTED I
r
(01)
CONTENTS OF c DATA BUS ARE LATCHED INTO MPU
PHASE 2 (02)
X\
Y2 DATA FROM LOCATION
ADDRESSED IS PLACED ON DATA BUS Fig. 9.9 Instruction register
sequence
Basic Microprocessors and the 6800
160
the falling edge of 2, the data
is
(Fig. 9.9) occurs every time the is
latched into the
MPU.
This general sequence
MPU addresses a memory location and data
transferred.
To tions by the
and
see
illustrate the role
of the system clock in the execution of instruc-
MPU, let us investigate several instructions from a simple program
what happens during each clock
Address
Contents
Description
Load A Immediate Data Load B Direct Address STA A Extended Address
100
86
101
25
102
D6
103
35
104
B7
105
40
106
02
1.
cycle:
Addresses 100 and 101 (two cycles):
Cycle
1: (a)
The contents of
the
P counter
(100) are placed on the
address bus. (b) (c)
The P counter is then incremented by 1 (to 101). The contents of address 100 (86) are placed on the data bus, latched into the
decoded as a load
VMA Cycle 2: (a)
A
MPU instruction register (IR), and Immediate instruction
(R/W
and
are "1").
The contents of
the
P
counter (101) are placed on the
address bus. (b) (c)
The P counter is then incremented by 1 (to 202). The contents of address 101 (25) are placed on the data bus and then latched into the
VMA are 2.
A accumulator (R/W and
"1").
Addresses 102 and 103 (three cycles):
Cycle
1: (a)
The contents of
the
P counter
(102) are placed in the
address bus. (b) (c)
The P counter is then incremented by 1 (to 103). The contents of address 102 (D6) are placed on the data bus, latched into the
coded as a load "1")
MPU instruction register,
and de-
B direct instruction (VMA and R/W are
M6800 Microcomputer Family Cycle 2: (a)
The
contents of the
address bus. (b) The P counter (c)
P
161
counter (103) are placed on the
then incremented by
is
1
(to 104).
The
contents of address 103 (35) are placed in the data bus and then latched into the address bus register
MPU
(VMA Cycle 3: (a)
and
R/W
are "1").
The contents of the address bus
register (35) are placed
on the address bus. (b)
The contents of address 35 then latched into the
B
are placed in the data bus
accumulator
(VMA
and
and
R/W
are "1").
3.
Addresses 104-106
Cycle
1: (a)
(five cycles):
The contents of
the
P counter
(104) are placed on the
address bus. (b) (c)
The P counter is then incremented by 1 (to 105). The contents of address 104 (B7) are placed on the data bus, latched into the
coded as a store
R/W Cycle 2: (a)
A
MPU instruction register, and deExtended instruction
(VMA
and
are "1").
The contents of
the
P
counter (105) are placed in the
address bus. (b) (c)
The P counter is then incremented by 1 (to 106). The contents of address 105 (40) are placed in the data
MPU temporary
bus and then latched into the
(VMA
(most significant byte) Cycle 3: (a)
The
contents of the
P
and
R/W
register
are "1").
counter (106) are placed on the
address bus. (b) (c)
The P counter is then incremented by 1 (to 107). The contents of address 106 (02) are placed on the data bus and then latched into the (least significant byte)
Cycle 4: (a)
The
(VMA
MPU address bus register and
R/W
are "1").
contents of the address bus register (4002) are
placed on the address bus. (b)
A accumulator (25) are readied for (VMA is "0" and R/W is "1"). Address 4002 is accessed, the R/W line is put in a low state (write), VMA is "1", and the contents of the A
The contents of the
transfer to the data bus
Cycle 5: (a)
accumulator are gated to the data bus and then stored in the address accessed (4002).
Basic Microprocessors and the 6800
162
9.3
Random Access Memory (RAM) 24
RAM
I
MCM68I0 2
AO
128x8
23
i
3
22
4
21
5
20
6
19
7
18
8
17
A6
9 10
16
R/W CSO
15
CS5
II
CS4
csi 12
14 13
CS3
Fig. 9.10
RAM
package
23.
AO
22
DO
THREE-STATE
MEMORY
ADDRESS DECODER
BUFFERS
(128x8)
FROMMPU ADDRESS LINES
^3
BIDIRECTIONAL
MATRIX
^4
20
j
5
TO MPU DATA LINES
s
AO-A6
^6
D0-D7
^7 ^8
A6
9
D7
CS5
O
CS4
CS3
FROM MPU \ CS2 AODRESS LINES
CSI
CSO
^
16
R/W
Fig. 9.11
The
(RAM).
It is
MEMORY CONTROL
M
7zr.
FROM MPU R/W
-i-o
READ/WRITE CONTROL
MCM6810 RAM
functional block diagram
MCM6810 is a TTL compatible, static Random Access Memory a three-state N-MOS chip containing 128 eight-bit words (128
bytes) housed in a 24-pin package (Fig. 9.10).
The
eight
RAM data bus pins,
DO through D7, are tied to the MPU data bus pins, DO through D7. The seven lines
an
AO through
eight-bit
word on
MCM6810 RAM
RAM
(AO through A6) must be tied to A6. These seven address lines are used by the
address pins from the
the particular chip addressed. If there
in the system, all
AO's are
tied to the
AO
is
MPU address MPU to select more than one
address line from
163
M6800 Microcomputer Family the
MPU, all Al's are tied to the Al
address line from the
MPU, and so forth.
RAM also has six chip select pins. These chip selects will be tied to the address bus from the MPU in such a manner that only one RAM addressed at a time. To address an MCM 6810 RAM requires a low chip
The MCM6810 is
on four of the chip selects and a high level on two of the chip selects. The addressing scheme for connecting the chip selects to the address bus will be covered in greater detail in Chap. 10. The read/write (R/W) line is the same
level
R/W from the MPU discussed in Sec. 9.2. To read data from a RAM location, the R/W line must be in a high state; to store data in a RAM location, the R/W line must be in a low state. When a RAM is not addressed, the RAM data bus goes to the three-state condition (high impedance).
A functional diagram of the MCM6810 RAM is shown in Fig. 9.4
9.11.
Read Only Memory (ROM) GND DO
ROM MCM6830
A0
24 23
1024x8
22 21
20 19 18 17 16
D7 15
CS0
A9 14
CSI
CS3
+5V
CS2
Fig. 9.12
ROM
13
package
The MCM6830 is a TTL compatible, mask-programmable Read Only
Memory (ROM).
It is
a three-state
N-MOS
chip containing 1024 eight-bit
ROM
data bus words (bytes) housed in a 24-pin package (Fig. 9.12). The eight pins, DO through D7, are tied to the MPU data bus pins, DO through D7. The ten address pins from the ROM (A0 through A9) must be tied to the MPU address bus pins, A0 through A9. These ten address lines are used by the MPU to select an eight-bit word on the particular chip addressed. If there is more is tied to the in the system, the A0 of each than one MCM6830
ROM
ROM
A0
MPU, the Al of each ROM is tied to the Al line in the MPU, The MCM6830 ROM has four chip selects available. These four
line in the
and so
forth.
chip selects must be denned by the user as to
and how many negative (CS). Since
how many
this device is
will be positive (CS) mask-programmable, the
164
Basic Microprocessors and the 6800
chip selects will be manufactured into the device. They will be tied to the address bus from the in such a manner that only one is addressed
MPU
at a time.
To select a ROM,
ROM
a
+ 2-V (or greater) signal must be applied to each
positive chip select (CS) and a 0-V level to each negative one (CS). The addressing scheme for connecting the chip selects to the address bus will be covered in great detail in Chap. 10. When a is not addressed, the
ROM
ROM
data bus goes into the three-state condition (high impedance).
A functional diagram of the MCM6830 ROM is shown in Fig. A0Al
FROM MPU ADDRESS LINES
A0-A9
24.
—
A2A3A4-
MEMORY
ADDRESS DECODER
MATRIX
THREESTATE BUFFER
-»*DI
*»D2
(1024x8)
+*D2
20,
*>D4
,
^
A5-
-^•05
—
•06
A6
9.13.
A7A8- -IV A9-
TO MPU DATA LINES
DO -07
-*»D7
CSO*-
FROM MPU CSI*ADDRESS < CS2*
LINES
CS3
14
•CHIP SELECTS ACTIVE LEVEL DEFINED BY USER
Fig. 9.13
MCM6830 ROM
9.5 Peripheral Interface
functional block diagram
Adapter (PIA)
The MC6821 Peripheral Interface Adapter (PIA) is an N-MOS device housed in a 40-pin package and used as a means of interfacing peripheral equipment and external signals with the MPU (Fig. 9. 14). The PIA communicates with the MPU through the same eight-bit bidirectional data bus that the RAMs and ROMs share. The PIA has two separate eight-bit bidirectional peripheral data busses for interfacing to the outside world.
input/output lines
may
The
16 bidirectional
be programmed to act as either input or output
lines
(Fig. 9.15).
In addition to the 24 lines select pins
shown
in Fig. 9.15, there are three chip
(CSO, CS1, and CS2), a reset pin (RES), two interrupt pins
(IRQA
and IRQB), a read/write Pin (R/W), four control line pins (CA1, CA2, CB1, and CB2), an enable pin (E), two register select pins (RS0 and RSI), and two input power pins ( + 5 and ground), as shown in Fig. 9.16.
165
M6800 Microcomputer Family
The MC6821 PI A has two has a peripheral data
A side and a B side.
an
sides,
Each
a data direction register, and a control
register,
side
register.
Each peripheral data register is the interface register between the PI A. chip and the outside world. This register
eight bits (one byte) wide.
is
used by the programmer to define each peripheral line as an input or an output line. When each bit in this eight-bit
The data
8
direction register
DATA
8
is
DATA
CONTROL
LINES TO/FROM PERIPHERAL
LINES TO/FROM CONTROL LINES PERIPHERAL
LINES
i_± PAO
PA7
RS0*0
PERIPHERAL
RSI
DATA
CRA2
REGISTER A
RSI =0 CRA2=(
RES Tl i
RS0=
=
1
CRB2
=
RS0
=
O
RSI -
1
I
1
DO
I
1
f
1
\
I'
I
KZ
CONTROL
RS0=
1
REGISTER B
RS1 =
1
R SI
E
IR QB
R SO
i L
J
PWR (+51
C 30
C 31 CS i
i i
i
I
1
1 f
f
/
..
I
I
i
READ OR
P|A
1
CRB2=0
REGISTER B
=
07
R/W
r
RESET
=
I
RS1
RS0 RS1
DATA
DATA DIRECTION
REGISTER A
REGISTER A
=
PERIPHERAL REGISTER B
RSO
CONTROL
INTERRUPT A TO MPU
=
DATA DIRECTION
TTT
RQA
=
ENABLE
DATA
WRITE
8
FROM MPU
TO/FROM MPU
LINES
Fig. 9.14
x
'
INTERRUPT B TO MPU
REGISTER SELECT
CHIP
FROM MPU ADDRESS
FROM MPU ADDRESS
LINES
LINES
MC6821
PI
SELECT
A
PIA
PERIPHERAL INPUT/OUTPUT LINES (ASIDE)
DATA LINES >-
Fig. 9.15
MC6821 PIA
input/output lines
TO/FROM MPU DATA BUS
166
Basic Microprocessors and the 6800
Fig. 9.16
register
output as
is set
line;
an input
MC6821 package
to a "1", the corresponding peripheral data line
when set to a "0",
The is
control register
is
used to permit the
register
PIA
is
is
defined
is
MPU to control the opera-
CA1, CA2, CB1, and CB2. This
also used to control the interrupt lines
interrupt flags. Bit 2 of this register selects, to
defined as an
line.
tion of the four peripheral control lines register
is
the corresponding peripheral data line
and monitor the status of the
used, in conjunction with the register
determine whether the peripheral data register or the data direction to be addressed.
Interface Lines
1. Peripheral Data Lines PAO through PA7 Each of these eight data lines interfacing with the outside world can be programmed to act as either an input or an output by setting a "1" in the corresponding bit in the data direction register (DDR) if the line is to be an output or a "0" in the
DDR
if it is
the
to be an input.
When
the data in the peripheral data lines
is
read into
MPU by a load instruction, those lines which have been designated as input
lines (0 in
DDR)
will
be gated directly to the data bus and into the register
167
M6800 Microcomputer Family
MPU. In TTL load.
selected in the
one standard
On
the input mode, each line represents a
the other hand,
when an output data
maximum
(STA
instruction
of
A PIA) is
executed, data will be transferred via the data bus to the peripheral data
A "1" output will cause a "high" on the corresponding data line, and will cause a "low." Data in peripheral register A that has been programmed as output may be read by an MPU "LDA A from PIA" instrucregister.
a "0" output
"1" or below 0.8 V for a logic "0", the data will agree with the data outputted. However, if these output lines have been loaded so that they do not meet the levels for logic "1", the data read back into the MPU may differ from data stored in PIA peripheral register A. tion. If the voltage is
above 2
V for a logic
Peripheral Data Lines
2.
PB7 B side may
PBO
on the as an input or output by setting a "1"
interfacing with the outside world
act either
the data direction register
DDR
if it is
to be
(DDR)
the line
if
eight data lines
programmed
to
corresponding
bit in
an output or a "0"
in the
in the
to be
is
also be
output buffers driving these lines have
an input. The
three-state capability, allowing
The
through
them
when the
to enter a high-impedance state
Data in peripheral register B that has peripheral data line is used as an read by an MPU "LDA A from PIA" programmed output may be been as instruction even though the lines have been programmed as outputs. If a line "1" in data direction register is first programmed as an output line by storing a B and then storing a "1" in that same bit position in peripheral data register input.
B, reading the bit status back will indicate a "1" even though excess loading
due to a short) may have occurred at the pin. This is because of the and the output pin. The eight bidirectional data lines 3. Data Lines (DO through D7) permit transfer of data to/from the PIA and the MPU. The MPU both sends and receives data to and from the outside world through the PIA via these eight data lines. The data bus output drivers are three-state devices that remain
(possibly
buffering between the register
in the
high-impedance
(of!) state
except
when
the
MPU performs a PIA Read
operation. 4.
Chip Select Lines (CSO, CS1, CS2)
address lines of the
MPU.
It is
These
lines are tied to the
through them that a particular
PIA
is
selected
For selection of a PIA, the CSO and CS1 lines must be high and the CS2 must be low. After the chip selects have been addressed, they must be held in that state for the duration of the E (Enable) pulse, which is the only timing signal supplied by the MPU to the PIA. This enable pulse (E) is (addressed).
normally the
VMA
line, 5.
2) signal if the device has been selected. A high on the Read/Write line sets up the PIA controls the direction of the data transfers
for a transfer of data to the data bus
when
are enabled
transferring data to the 8.
circuitry, are
Read).
The PIA output
buffers
MPU.
Interrupt Request Lines
MPU
interrupt the
(MPU
the proper address and the enable pulse are present, thus
(IRQA and IRQB)
These
lines,
which
either directly or indirectly through interrupt priority
"open source" (no load device on the chip). They are capable of from an external source, thereby permitting all
sinking a current of 1.6
mA
OR"
interrupt request lines to be tied together in a "wired
configuration.
Interrupts are serviced by a software routine that sequentially reads and tests,
on a
priority basis, the
two control
6 and 7) that are
bits (bits
set.
registers in
each
PIA
for the interrupt flag
(These control registers and the way in which
When
the flag bits get set will be discussed shortly.)
the
MPU
reads the
peripheral data register, the interrupt flags (bits 6 and 7) are cleared and the interrupt request
is
cleared.
These request lines (IRQA and IRQB) are active when low. 9. Interrupt Input Lines (CA1 and CB1) These lines are input only to the PIA and set the interrupt flag (bit 7) of the control registers in the PIA. Discussion of these lines in conjunction with the control register will follow.
This line can be programmed
Peripheral Control Line (CA2)
10.
to act either as an interrupt input or peripheral output.
As an
output,
compatible with standard TTL, and as an input, represents one standard load. 4,
The
and
function of this line
programmed with
control register
A (bits
3,
5).
Peripheral Control Line (CB2)
11.
grammed
This line
to act as an interrupt input or peripheral output.
greater than
TTL. As an
1
-megohm
output,
as a source of
up
switch directly.
B
is
it is
TTL
(bits 3, 4,
to
The
and
it is 1
input impedance and
may also be proAs an input, it has
is
compatible with standard
compatible with standard
TTL and may also be used
mA at
1.5
V
and thus
function of this line
is
to drive the base of a transistor
programmed with
control register
5).
Addressing
To access a PIA, a high state ("1") must be applied to CSO and CS1 while a low state ("0") is applied to CS2. The RSO and RSI pins are tied to
M6800 Microcomputer Family
1
69
MPU address lines A0 and Al, respectively. Once the PI A has been accessed, RSO and RSI
the
in the
PIA.
lines?
This
input pins are used to select one of the six internal registers
How is it possible to select one of six registers with only two input is
the only purpose of bit 2 of the central registers. If bit 2 of control
A (CRA) is a "0", and RSO and RSI (from A0 and Al) are also "0", then data direction register A (DDRA) is addressed. The level of each bit in data direction register A (DDRA) defines whether each corresponding line of peripheral data register A is an input (if a "0") or an output (if a "1"). The register
following sequence of instructions will define bits
data register
A (PDRA)
through 4 of peripheral and bits 5, 6, and 7 of this same register 4004 through 4007).
as inputs,
PIA
as outputs (address of the
is
Address
Contents
100
86 11100000
LDA A
#%
101
102
B7
STA A
$4004
103
40
104
04
Description
11100000
The above series of instructions would be part of the initialization program that would be run after applying power since the control register has selected the DDR as opposed to the output register. The next step after defining the individual peripheral lines on the A side of this
PIA as inputs or outputs is to load a " 1" into bit 2 of control register
A (CRA). Normally, the remaining bits of this register would have data loaded into
them during
Since bit 2
we
is
this
same
operation, but this matter will be discussed later.
the only bit of control register
A (CRA) that affects addressing,
will look at bit 2 only rather
than complicate the issue at this time. If the previous example were continued, it might look as follows:
Address
Contents
105
86
106
00000100
107
B7
108
40 05
109
This will store a "1" in
Description
LDA A STA A
#% 00000100 $4005
bit 2 of control register A (CRA). Once it has been loaded, addressing hex location 4004, as we did initially, will access peripheral data register A (PDRA).
1
Basic
70
M icroprocessors and the 6800
To summarize, using the above example, addressing hex location 4004
MPU to communicate with data direction register A (DDRA) if A (CRA) a "0". After this bit is put at a "1", addressing hex location 4004 allows the MPU to communicate with peripheral data register A (PDRA): allows the
2 of control register
bit
is
Summary of A
CRA
RS0
RSI
Side Addressing Register Selected
(Bit 2)
Data Doesn't matter
1
Addressing on the
be high while CS2
B
side
A
A A
Peripheral data register
1
NOTE: CS0 and CS1 must
direction register
Control register
is
A side.
To address data direction "0" and RSI is set to a "1" while
handled in
is
low.
much
B (DDR
register
the
same way
RS0
B),
is
as
on the
set equal to
a
B (CRB) is held at "0" level. After the individual bits in data direction register B (DDRB) are a loaded with "Is" or "0s" to define the individual peripheral data register B lines as inputs and outputs, a "1" is stored in bit 2 of control register B by setting RS0 to a "1" and RSI to a "1". After the "1" has been stored in bit 2 of CRB, peripheral data register B will be addressed whenever RS0 is a "0" and RSI
is
bit
of central register
a "1".
Summary of B
CRA
RS0
RSI
1
Side Addressing Register Selected
(Bit 2)
Data
1 1
1
direction register
Control register
Doesn't matter
1
Peripheral data register
1
B
B
B
To summarize, one of the functions of the initialization program that be run immediately after powering up is to configure the PIAs. The side as inputs and lines 4-7 following program would define lines 0-3 of the will
A
of the
B
on both sides would be outputs: Hex 4004-4007 A Side: lines 4-7
side as inputs; the remaining lines
PIA
Address:
Output Lines: Input Lines:
B
Side: lines
A
Side: lines
B
Side: lines
0-3 0-3 4-7
M6800 Microcomputer Family Address
171
Contents
Description
LDA B IMMED
100
C6
101
11110000
102
F7
STA B EXTENDED
103
40 04
DDR A
105
C6
LDA B IMMED
106
00001111
107
F7
STA B EXTENDED
108
40 06
LOADS
104
109
LOADS
11110000
IN
00001111
DDR B LDA B IMMED IN
10A
C6
10B IOC
00000100
F7
STA B EXTENDED
10D
40 05
SETS BIT 2 IN CRA TO
F7
STA B EXTENDED
40 07
CRB TO A
10E 10F 110 111
SETS BIT
CONTROL REGISTER A 7
6
IRQA1
IRQA2
CA1 Control
(Bits
5
4
.
CA2
and
3
"1"
IN "1"
(CRA) 2
1
DDRA
Control
2
A
CA1
Control
1)
Peripheral control line
CA1
is
an input only
line. It
may
be used to
cause an interrupt by setting the interrupt flag IRQA1 (bit 7) of control register A. Bits and 1 of are used to determine how the interrupt is to be
CRA
The IRQA1
handled.
flag (bit 7)
of
CRA will get set to a "1"
only under the
following conditions:
is
1.
A negative transition on the CA1
2.
A
line is detected
and
bit
1
of
CRA
a "0". rising transition
on the
CA1
is
detected
and
bit
1
of
CRA
is
a
"1". (All other combinations will be ignored.)
Whether the IRQA1
flag is
permitted to pull the
interrupting the MPU, depends upon the status of bit a "0", the interrupt will be masked (disallowed).
Peripheral control line
CA1
is
summarized
in
IRQA line low,
of
CRA.
Table
thus
If this bit is
9.2.
Basic Microprocessors and the 6800
172
Summary
Table 9.2
of
CM
Control Status of
Transition of
Status of
interrupt
bit 1 in
input line
CRA
CA
bit
CRA
(edge)
IRQA
IROA1
Status of
(interrupt flag)
in
(mask)
Bit
line
(MPU interrupt
7 of CRA
request)
Masked
1
(remains high)
Goes low (processor interrupted)
Masked (remains high)
Goes low (processor interrupted)
Remains high Remains High
DRA
is the IRQA1 interrupt "mask of seen in Table 9.2, bit bit." If bit is a "0", setting the interrupt flag IRQA1 will not contains a "1", the IRQA cause the interrupt line IRQA to go low. If bit line will be permitted to go low when IRQA1 gets set to a "1".
As
programming
Bit
1
of
CRA is the "edge programming bit." A "0" in bit
the interrupt flag the
CA1
bit
CRA
and a "1"
line,
transition.
IRQA1
(NOTE:
(bit 7) to get set to
in bit
If the
1
programs the flag to get set to a "1" in a positive flag was set to a "1" during a period when
Data Direction Register (DDR A) bit, in
programs
IRQA1
had masked all interrupts, the interrupt is changed to a "1" by the MPU.)
This
1
a "1" in a negative transition of
will
be allowed when
of
bit
(Bit 2)
conjunction with register select lines
RSO and RSI,
is
used
to select either the peripheral data register or the data direction register, as
follows:
RSI
RSO
CRA
(Bit 2)
Register Selected
A
Data Direction Register 1
Doesn't matter 1
Control Register
A
Peripheral Data Register
A
.
M6800 Microcomputer Family
CA2
Control (Bits
and
3, 4,
As mentioned
5) can be programmed to function as an
earlier, this line
interrupt input line or a peripheral output line.
A determine how
of control register the
CA2
it
will
The
status of bits 3, 4,
and
5
to function. Bit 5 determines whether
be used as an interrupt
be used as an output
will
it is
be an interrupt input line or a peripheral output
line is to
5 contains a "0", it
173
line; if bit 5
line. If bit
contains a "1",
line.
CA2 As an Interrupt Input Line (Bit 5 = "0") Bits 3 and 4 how the interrupt is to be handled. The IRQA2 flag (bit 6) of CRA
determine will
be
set to
a "1" only under the following conditions:
A negative transition on the CA2 line is detected and bit 4 is a "0". 2. A rising transition on the CA2 line is detected and bit 4 is a "1". 1
(All other combinations are ignored.)
The CA2
control
is
summarized
Table 9.3
Summary
in
of
Table
CA2
9.3.
Control
IRQA2
Status of bit
Transition of
input
CA2
CRA
5 in
Status of
(I/O
control)
bit
CRA
4
in
(edge)
Status of
(interrupt
3
flag)
bit
CRA
(Mask)
~T_
"
in
Bit
6 of CRA 1
Status of
IRQA
line
(MPU interrupt request)
Masked (remains high)
L
1
1
Goes low (processor interrupted)
-J_
1
1
Masked (remains high)
j~
1
1
1
Goes low (processor interrupted)
~L _r
— —
1
Remains high
Remains high
CRA
As
seen in Table 9.3, bit 3 of is the interrupt "mask programit is a "0", setting the interrupt flag IRQA2 will not cause interrupt line IRQA to go low. If it is a "1", the IRQA line will be permitted to go low when IRQA2 gets set to a "1".
ming
bit." If
Bit 4 of
interrupt flag
CRA is the "edge programming bit." A "0" in bit 4 programs
IRQA2
(bit 6) to get set to
a "1" on a negative transition of the
Basic Microprocessors and the 6800
174
GOES LOW WHEN
r- GOES HIGH ON TRANSITION
OATAONASIDE
CAI INTERRUPT \(IROAISETTO"l")
\ OF
/HAS BEEN READ BY MPU DURING FALLING EDGE OF ENABLE SIGNAL (0 2) (LOAD A FROM PIA)
CA2 LINE
NORMALLY LOW THIS
MODE
INv
\
^_n_rL TIME
PERIPHERAL SAYS, "HELLO MPU, I HAVE SOME DATA FOR YOU."
I
PERIPHERAL
PIA
/ 1
CAI
"o"
CA2
PERIPHERAL
TIME 2
PIA IROAI
= "l"
"
CA2
i
TIME 3
MPU SAYS, "IGOT YOUR MESSAGE"
PIA
PERIPHERAL
"0"
m
IR0AI»"0" (UPON MPU READ) CA2
^MPU SAYS, "OK PERIPHERAL, I GOT YOUR INPUT DATA, I'M READY FOR MORE."
Fig. 9.17
A
Handshake mode
4 programs the flag to get set to a "1" on a rising IRQA2 flag was set to a "1" during a period when bit 4 had masked all interrupts, the interrupt will be allowed when bit 4 of CRA is changed to a "1" by the MPU.
CA2
line.
transition.
"1" in
NOTE:
bit
If the
CA2 As an Output Line a "1", the
CA2
(Bit
an output, the IRQA2 flag remains high. As an output,
(bit it
5 = "1 ") an output
If bit 5 of
CRA
is
set to
Whenever it is used as 6 of CRA) remains a "0" and the IRQA
line is designated as
line.
has four options:
1
M6800 Microcomputer Family Bits
1.
shake
mode
peripheral
is
must
the peripheral is
5, 4,
=
and 3 ofCRA
used when a peripheral
MPU when
the
tell
when
it
it
175
100 (Handshake Mode) is
The hand-
transmitting data to the
has some data, and the
MPU. The
MPU must tell
has taken the data (see Fig. 9-17). The typical sequence
as follows: (1) Peripheral
sends signal via interrupt line
A, which
7) of control register
(2)
MPU. When the IRQA1
(3)
After the
tells
the
CA1
IRQA1
to set
MPU
it
flag (bit
has data to give to
the
MPU
flag gets set to
CA2
line
goes high.
reads the contents of peripheral register
CA2
from PIA), the
a "1", the
A
(load
A
go low. This signals the peripheral that the MPU took the data and is now ready for more. 2. B^s 5, 4, and 3 ofCRA = 101 (Pulse Mode) This mode, which tells the peripheral that the data on peripheral data register A has been read by the MPU, is used when a complete handshake is not required. The peripheral may make data available to the MPU on a continuing basis but needs to
know when
the
MPU
line will
takes the data (see Fig. 9.18).
GOES LOW AFTER A "READ A SIDE OATA" INSTRUCTION
CA2 NORMALLY HI6H IN THIS MOOE
GOES HIGH ON THE NEGATIVE EDGE OF THE NEXT E SIGNAL AFTER THE READ A SIDE DATA INSTRUCTION
— ENABLE
'
SIGNAL I
(0 2)
MPU SAYS, "HEY PERIPHERAL,
PERIPHERAL
tJ" Fig. 9.18 Pulse
Bits
3.
line will
5, 4,
and 3 ofCRA
always be in the low
=
and 3 ofCRA always be in the high state.
Interrupt Flag Bits
As Flag
110
In this mode, the
CA2
output
111
In this mode, the
CA2
output
(IRQA1 and IRQA2)
already seen, bits 6 and 7 of control register
interrupt occurs. Flag bit line.
mode
state.
4. Bits 5, 4,
line will
=
CA2
bit
IRQA2
IRQA1
(bit 6) is
(bit 7) is
A
get set
the interrupt bit for the
the interrupt bit for the
CA2
when an
CA1
input
input
line.
The
Basic Microprocessors and the 6800
176
only lines.
way that these bits can get set is via the CA1 and CA2 interrupt input The MPU cannot store a "1" in these two locations, but it can read their
When
status.
the
and 7 of that
MPU
reads the status of peripheral data register A, bits 6
be cleared ("0").
register will
Control Register
CBI
7
6
IRQBI
IR0B2
5
CB2
and
Control (Bits
4
|
B (CRB) 3
|
2
1
DORB
Control
CBI Control
1)
Peripheral control line
CBI
is
an input only
line that
IRQBI (bit 7) determine how the
cause an interrupt by setting interrupt flag
and
B. Bits
handled.
1
of
CRB
The IRQBI
are used to
flag (bit 7)
of
CRB will
may be
used to
of control register is to be under the
interrupt
get set to a "1" only
following conditions:
is
1.
A negative transition on the CBI
2.
A
and
line is detected
bit
1
of CRB
a "0". rising transition
on the CBI
is
detected
and
bit
1
of
CRB
is
a
"1". (All other combinations will be ignored.)
Whether the IRQBI
flag is
Table 9.4
permitted to pull the
Summary
of
IRQB line low,
thus
CB1 Control Status of
Transition of
Status of
interrupt
bit 1 in
input line
CB1
CRB
(edge)
IRQB1
Status of bit
in
CRB (mask)
(interrupt flag)
Bit
7 of CRB 1
IRQB
Line
(MPU interrupt request)
Masked (remains high)
Goes low (processor interrupted)
Masked (remains high)
Goes low (processor interrupted)
Remains high
Remains high
M6800 Microcomputer Family
MPU,
interrupt ing the
"1", the
IRQB
depends on the status of bit of CRB. go low, causing the interrupt. If it
line will
interrupt will be
masked
The CB1 control As seen in Table programming
bit." If bit
cause the interrupt line line will
1
77
If the bit is a is
a "0", the
(disallowed). is
summarized of
9.4, bit is
in
Table
CRB
9.4.
IRQB1
the
is
interrupt
a "0", setting the interrupt flag
IRQB
to
go low.
be permitted to go low when
IRQB1
contains a "1", the gets set to a "1".
If bit
IRQB1
"mask
will
not
IRQA
programming bit." A "0" in bit 1 programs the interrupt flag IRQB 1 (bit 7) to get set to a "1" on a negative transition of the CB1 line. A "1" in bit 1 programs the flag to get set to a "1" on a positive transition. (NOTE: If the IRQB1 flag was set to a "1" during a period when bit had masked all interrupts, the interrupt will be allowed when bit of CRB is changed to a "1" by the MPU.) Bit
of CRB
1
is
the "edge
Data Direction Register This
B (DDRB)
(Bit 2)
conjunction with register select lines
bit, in
RSO and RSI,
is
used
to select either the peripheral data register or the data direction register.
10
RSI
RSO
1
1
CRB
Data Doesn't matter
1
CB2
Register Selected
(Bit 2)
As mentioned
3,
4y and
B
earlier, this line
determine
can be programmed to function as an
how
the
CB2
mines whether
it
will
be an interrupt input
contains a "0",
it
will
be an interrupt
an output
The
1.
2.
line
or an output
line. If bit 5
Interrupt Input Line (Bit 5
are used to determine
flag (bit 6)
status of bits 3, 4,
and
5
line is to function. Bit 5 deterline. If bit
contains a "1",
it
will
5
be
line.
CB2 As an
CRB
B
5)
interrupt input line or a peripheral output line.
of control register
B
B
Peripheral data register
1
Control (Bits
direction register
Control register
of
CRB
how
the interrupt
will get set to a
is
=
"0")
Bits 3
to be handled.
and 4 of
The IRQB2
"1" only under the following conditions:
A negative transition in the CB2 line is detected and bit 4 is a "0". A rising transition in the CB2 line is detected and bit 4 is a "1".
All other combinations are ignored.
The CB2 control is summarized in Table 9.5. As seen in Table 9.5, bit 3 of CRB is the interrupt "mask programming bit".
If bit 3
is
a "0", setting the interrupt flag
IRQB2
will not cause the
Basic Microprocessors and the 6800
178
Summary
Table 9.5
of
CB2
Control
IRQB2
Status of
(interrupt
/ROB line (MPU interrupt
Status of bit
CB2
Status of
Status of
CRB (I/O
Transition of
input
5 in
bit
4
in
bit
CRB
CRB (edge)
control
3
in
(mask)
flag)
Bit
6 of CRB
request)
Masked (remains high)
Goes low (processor interrupted)
Masked (remains high)
Goes low (processor interrupted)
Remains high Remains high
interrupt line
IRQB
to
go low.
If
it
contains a "1", the
when IRQB2 gets set to a "1". Bit 4 of CRB is the "edge programming bit".
IRQB
line will
be
permitted to go low the interrupt flag
the
IRQB2
(bit 6) to get set to
A "0" in bit 4 programs
a "1" on a negative transition of
CB2 line. A "1" in bit 4 programs it to get set to a "1" on a rising transition. If the IRQB2 flag was set to a "1" during a period when bit 3 had
(NOTE: masked
all interrupts,
the interrupt will be allowed
changed to a "1" by the
when
bit 3
of
CRB
is
MPU.
CB2 As an Output Line (Bit 5 = "1") If bit 5 of CRB is set to CB2 line is designated as an output line. Whenever it is used as an output, the IRQB2 flag (bit 6 of CRB) remains a "0" and the IRQB remains high. As an output, it has four options:
a "1", the
1.
is
used
tell
Bits
when
the
MPU
and 3 of CRB = 100 (Handshake Mode) This mode MPU sends data to a peripheral device. The peripheral must is ready for the data. After the MPU sends the data to
5, 4,
the it
peripheral data register B,
data
is
request 9.19)
is
it
sends a signal to the peripheral telling
it
that the
available at that register. After the peripheral takes the data,
more data, and the sequence is repeated. The
it
can
typical sequence (see Fig.
as follows:
(1) In order to tell the
MPU that
a signal via interrupt line register B.
it
CB1
wants some data, the peripheral sends
to set the
IRQB1
flag (bit 7)
of central
M6800 Microcomputer Family (2)
When
the
(3) After the line will
IRQB1
flag gets set to
179
a "1", the
CB2
goes high.
line
MPU sends the data to peripheral data register B, the CB2
go low, thereby signaling the peripheral that the data
is
there
for the taking.
COES HIGH ON TRANSITION OF CBI INTERRUPT (IROBI SET TO "1")
STORES DATA IN THE PERIPHERAL DATA REGISTER B
V
MODE
THIS
ENABLE
'SIGNAL AFTER MPU
\
CB2 NORMALLY LOW IN
GOES LOW ON FIRST .POSITIVE OF
ENABLE SIGNAL (02)'
TIME
PERIPHERAL SAYS, "HELLO MPU, NEED SOME DATA* I
I
PERIPHERAL
PIA
v
/
_
CBI
CB2
MPU
SAYS,
I
GOT YOUR MESSAGE"
TIME 2
PERIPHERAL
PIA
/ »
/ "/
• IRQBI="f CB2
TIME 3
PERIPHERAL
PIA
IRQBI-"0" M
o"
CB2
^MPU SAYS, OK PERIPHERAL, HERE IS YOUR DATA ON MY PERIPHERAL DATA REGISTER 8"
Fig. 9.19
2.
Bit 5,3
ofCRB
the peripheral that data
is
=
Handshake mode
101 (Pulse Mode)
This
mode
is
used to
tell
available in
PIA
=
110
In this mode, the
CB2
output
=
111
In this mode, the
CB2
output
peripheral data register
B (see Fig.
9.20). 3.
line will
5, 4,
and 3 ofCRB state.
Bits 5, 4, and 3 ofCRB always be in the high state.
4.
line will
Bits
always be in the low
1
Basic Microprocessors and the 6800
180
.
GOES LOW ON THE POSITIVE TRANSITION ON THE FIRST ENABLE (01) PULSE AFTER THE STORE DATA IN PERIPHERAL DATA REGISTER B INSTRUCTION
CB2 NORMALLY HIGH IN THIS
—
CB2
ENABLE SIGNAL
—
r-GOES HIGH ON THE NEXT POSITIVE ENABLE \ (02) AFTER THE "STORE DATA IN \ PERIPHERAL REGISTER B" INSTRUCTION
MODE
f
(0 2)
"HEY PERIPHERAL, itta URiM run 1
/
PERIPHERAL
PIA
ilr CB2
mode
Fig. 9.20 Pulse
Interrupt Flag Bits
(IRQB1 and IRQB2)
A
get set already seen, these two bits (6 and 7) of control register when an interrupt occurs. Flag bit IRQB (bit 7) is the interrupt bit for the CB1 input line. Flag bit IRQB2 (bit 6) is the interrupt bit for the CB2 input line. The only way these bits can get set is via the CB1 and CB2 interrupt input
As
lines.
The
status.
MPU cannot store a "1" in these two locations, but
When
it
control register
can read their reads the status of peripheral data register B, bits 6 and 7 of
B
will
it
be cleared ("0").
PIA Summary 1.
Register Selects
(b) If
RSI RSI
(c) If
RSO
(a) If
RSI and RSO
is
set to
a "0", then the
A
side of the
is
set to a "1", then the
B
side of the
is
set to
a "0" and
peripheral data register (d) If
RSO
is
set to a
direction register (e) If 2.
to a "0",
is
CRA
bit 2 is a "1",
then the
(or
CRB)
is
a "0", then the data
selected.
RSO is set to a "1", then the CA1 or CB1 Interrupt Lines all
CRB)
(or
selected.
"0" and is
CRA
PIA is selected. PIA is selected.
interrupts caused by
CA1
control register If bit
(or
CB1)
of are
is
selected.
CRA
(or
CRB)
is
set
masked by the PIA.
However, the interrupts flags will still get set if the proper transition occurs on CA1 (CB1). If bit of CRA (or CRB) is set to a "1", all interrupts caused by CA1 (or CB1) will be allowed to interrupt the MPU.
M6800 Microcomputer Family
CA2 or CB2 Interrupt Line
3.
a "0", and
=
"0",
If bit 3 of
181
CRA (or CRB) is set to
CA2
(or CB2) are masked by the PIA. However, the interrupt flags will still get set if the proper transition occurs on CA2 (or CB2). If bit 3 of CRA (CRB) is set to a "1", all interrupts by CA2 (or CB2) will be allowed to interrupt the MPU. bit 5
all
interrupts caused
by
= "1", then the CA2 (or CB2) lines are used as outputs. IRQA1, IRQA2, IRQB1, IRQB2 Flag Bits These bits (bits 6 and 7 of CRA & CRB) are read only bits. The MPU cannot write into them, and only interrupts from the outside world can set them. They will be cleared only when the peripheral data register is read or there is a hardware reset. 5. Control Registers CRA and CRB Control registers CRA and CRB have total control of CA1, CA2, CB1, and CB2 lines. The status of all If bit 5
4.
eight bits
through
may be
MPU,
read into the
although
it
can only write into
bits
5.
6.
Addressing
Before addressing PIAs, the Data Direction Regiswith the bit pattern that defines how each line
(DDR) must first be loaded
ter
A
is to function, that is, as an input or output. logic "1" in the register defines the corresponding line as an output, and a logic "0" defines it as an input. Since
DDR
the
and the peripheral data register have the same address, control which is being addressed. If bit 2 is a logic "0", then
register bit 2 determines
the
DDR
is
addressed;
addressed. Therefore,
if it is
it is
a logic "1", the peripheral data register
essential that the
is
DDR be loaded before setting bit
2 of the control register.
The above sequence of outputs of the
PIA
setting
up the PIA assumes
are active high (True
that the data
2.4 V).
7. PIA—After Reset When the RES (Reset Line) has been held low for a minimum of eight machine cycles, all registers in the PIA will have been cleared. Because of the reset conditions, the PIA has been defined as
follows:
I/O lines to the "outside world" are defined as inputs. CA1, CA2, CB1, and CB2 are defined as interrupt input lines that are
(1) All (2)
negative-edge sensitive. (3) All interrupts bits will
Active
Low When
<
on th e control
not cause
IRQA
l
or
ines are
IRQB
masked. Setting of interrupt flag go low.
to
Outputs all
the outputs of a given
PIA
port are to be active low (True
0.4V), then the following procedure should be used: 1.
Set bit 2 in the control register.
($FF)
2.
Store
all l's
3.
Clear
bit
4.
Store
all l's
5.
Store control
in the peripheral data register.
2 in the control register.
($FF)
word
in the data direction register. (bit
2=1)
in the control register.
Basic Microprocessors and the 6800
182
The B
Example
PIA1
side of
set
is
up
to have
all
active
low
outputs. CB1 and CB2 are set up to allow interrupts in the handshake mode and CB1 will respond to positive edges (low-to-high transitions). Assume reset conditions. Addresses are set up and equated to the same labels as in the
previous example.
Set bit 2 in
3.
LDA A #4 STA A PIA1BC LDA B #$FF
4.
STA B PIA1BD
All
5.
CLR PIA1BC
Clear bit 2
6.
STA B PIA1BD
All
LDA A #$27 STA A PIA1BC
00100111
1.
2.
7. 8.
The above procedure
—
going low
is
l's in
(control register)
peripheral data register
data direction register
Control register
required in order to prevent outputs from
—
low True state when all l's are stored in the data would be the case if the normal configuration procedure as
to the active
direction register,
l's in
PIA1BC
were followed.
PIA Polling Routine one of the various techniques for determining which PIA has generated an interrupt. Recall that every PIA has an A side and a B side that may cause the IRQ line to go low, thus generating an interrupt. All PIA interrupt lines are tied together and connected to the one interrupt This routine
is
input pin (IRQ) of the
MPU.
Consequently,
when an
interrupt
is
generated,
a bit 6 or 7 of a PIA is set. The only way to determine where the interrupt came from is to poll bits 6 and 7 of every PIA control register to see which one is a "1" (and thus an interrupt).
This routine (see Fig. 9.21 for its flowchart) polls the control registers of two PIAs. It reads the contents of each control register and executes the BMI instruction that effectively checks on whether bit 7 is set. If it is not set, a
ROL A
use of the
instruction
BMI
is
executed that shifts bit 6 into
instruction again.
Once a
bit 7,
thus permitting
set control bit is detected, the
processor branches to a subroutine to service that particular interrupt. After the interrupt has been serviced, an RTI instruction is executed that causes the processor to return to whatever
The source program
it
NAM POLL DPT MEM PIKlftC ECU *4005 PlftlBC EOU *4007 FIfi£*C EOU *4009 PIftcEC ECU M00K £00 OPS 1100 £10 POLL LDrt * PIftlftC ££0 BMI POUT1 100 110 1£0 130 140 150
was doing before the
for the
PIA
interrupt.
polling routine
is
as follows:
M6800 Microcomputer Family £3 £4
POL
ft
Bill
POU Ti-
£50 £60 £70 £3 £90 300
LDft
210 320 330
POL
34
350 360 37
ft PIftlBC EMI POUT 3
POL
ft
BMI P0UT4 LDft
ft
PIfl£ftC
BMI P0UT5 ft
BMI POUT* LDft ft PIft2BC BMI P0UT7
POL
ft
BMI POUTS PTI
HOP
THIS
IS PIftlftC Cftl
SERVICE ROUTINE
400 POUT£ HOP 410 PTI 420 pout HOP
THIS
IS PIftlftC Cft2
SERVICE ROUTIME
THIS IS PIftlBC CB1
SEPVICE POUT I HE
380 ROUT 390 PTI
1I
:i
4 30
44
450 460 470 4S0 490 500 510 520 530 54
PTI
P0UT4 HOP
THIS
IS PIftlBC CB2 SEPVICE POUT I HE
THIS
IS PIft£ftC Cftl
SEPVICE ROUT I HE
THIS
IS PIftcftC Cft£
SEPVICE ROUTINE
PTI
POUTS HOP PTI POUT*> HOP PTI POUTT• MOP PTI
POUTS MOP
THIS IS PIft£BC CB1 SEPVICE POUT I HE
THIS
0100 0100 0103 0105 0106 0108 01 OB
0100 010E 0110 0113 0115 0116 0118 0111 0110 011E 0120 0121
0122 0123 0124 0125 0126 0127
IS PIft£BC CB2 SERVICE
POUTIME
PTI
MOM
The assembled program
00100 00110 00120 00130 00140 00150 00200 00210 00220 00230 00240 00250 00260 00270 00280 00290 00300 00310 00320 00330 00340 00350 00360 00370 00380 00390 00400 00410 00420 00430 00440
183
for the routine
MRU OPT 4005 PIftlftC EOU 4007 PIftlBC EOU 4009 PIA2AC EQU 400B PIA2BC EOU 0R6 B6 4005 POLL LDfl A 2B 1C BMI 49 RDL ft 2B IB BMI B6 4007 LDfl ft 2B 18 BMI 49 ROL A 2B 17 BMI B6 4009 LOft A 2B 14 BMI 49 ROL A BMI 2B 13 B6 400B LDfl A 2B 10 BMI 49 ROL ft 2B OF BMI RTI 3B ROUT1 NOP 01 RTI 3B R0UT2 NOP 01 3B RTI R0UT3 NOP 01 RTI 3B 01 R0UT4 NOP
is
as follows:
POLL MEM S4005 S4007 S4009 S400B S100 PIftlftC
RDUT1
R0UT2 PIA1BC R0UT3
R0UT4 PIA2AC ROUTS R0UT6 PIA2BC ROUT7 R0UT8
THIS
IS PIA1AC CA1 SERVICE
THIS
IS PIAIAC CA2 SERVICE
THIS
IS PIA1BC CB1 SERVICE
THIS
IS PIftlBC
CB2 SERVICE
Basic Microprocessors and the 6800
184
00450 00460 00470 00490 00490 00500 00510 00520 00530 00540
0129 3B 0129 01 012ft 3B 012B 01 012C 3B 012D 01 012E 3B 012F 01 0130 3B
RT1
ROUTS
HOP
ROUT6
MOP
THIS
IS PIft2ftC Cfll SERVICE
THIS
IS PIfl2flC CA2 SERVICE
THIS
IS PIR2BC CB1 SERVICE
THIS
IS PIR2BC CB2 SERVICE
RTI RTI
R0UT7
NOP RTI
RDUT9
NOP RTI
HON
SERVICE ROUTINES (CR7 SET)
PIA1AC PIA1BC PIA2AC PIA2BC
ROUT 1 ROUT 3 ROUT 5 ROUT 7
*0
SERVICE ROUTINES (CR6 SET)
PIA1AC PIA1BC PIA2AC PIA2BC
Fig. 9.21 Flowchart for
9.6
PIA
ROUT 2 ROUT 4 ROUT 6 ROUT 8
"©
polling routine
Asynchronous Communications Interface Adapter
MPU
communicates In the previous section, it was shown how the with the outside world via the PIA, through which data can be sent to or eight bits at a time in parallel. For this purpose, eight received from the
MPU
lines are
needed between the
When
it is
eight separate lines
PIA and
the peripheral (data).
necessary to send or receive data over very long distances,
must be run from the data
service to the
PIA. The Asyn-
M6800 Microcomputer Family
185
chronous Communications Interface Adapter (ACIA) permits data to be line, not the eight lines a PIA requires. The ACIA can function either as a serial-to-parallel converter or as a parallel-to-serial converter (Fig. 9.22). Data can be sent to the ACIA over the D0-through-D7 data lines; it is then converted to a series of l's and O's in the ACIA and sent out over a single line to a receiver. Likewise, data in the form of l's and O's can be received by the ACIA from an external source, transmitted in a serial format with only one
ACIA and sent to the MPU over the D0-through-D7 data lines. As one can well imagine, a great deal of bookkeeping must be done when data bits are transmitted or received in a serial format to resolve such questions as: (1) Where does each group of bits stop and the next group start? (2) How does the ACIA know when it is to receive or send data? (3) How does the ACIA detect if a bit is lost? These questions, and many others, will be answered in this section.
converted to a parallel format in the
General In any type of data communications, two terms are encountered
— that
synchronous and asynchronous
refer to the type of clocking used to
transfer the data. In synchronous transmission, the data rate
is
locked into the
system clocking. The receiver and the transmitter must be synchronized with each other since there
is
no two-way communication. Usually, one device MPU
ACIA
DO 1
DATA
07 1 06 1 DS| D4 j D3 02
1
PI
DO
I
IN
(A)
SERIAL TO PARALLEL MPU
ACIA
Dl
02 |D3 04 DSJD6|07| 1
DATA OUT
L t
(B)
Fig. 9.22
D7
D7
DO
DO
PARALLEL TO SERIAL
Conversion functions of the ACIA
will
Basic Microprocessors and the 6800
186
request
some data from the other
device, wait a fixed period,
and then read
the data (assuming that the data was placed on the bus during the waiting period). In asynchronous transmission, "start"
data
word
to let the receiver
and "stop"
the receiver detects the stop bit (end of data word),
next data word.
The data words
Baud rate often
is
the
number of data
The
Start Bit
from a "1"
bits.
This
is
first bit
is
Definitions of various bits follow.
of a serial data word that signals the start bits.
This
bit is usually detected as
a
to "0," referred to as a "mark-to-space" transition.
The
Stop Bit
last bit
of a serial data word that signals the end of
usually a high ("1") signal.
is
When transmitting a series of bits, it is common for the
Parity Bit
transmitter to add
Two
and parity
per second. Very often, the parity bit bit.
of transmission of a series of data
transmitted.
start, stop,
the same as "bits per second," a term that expresses only bits transferred
that word. This bit
then wait for the
A baud is defined as the reciprocal of the shortest pulse
included as an information or data
transition
will
are not locked into the system timing.
duration in a data word (signal), including
mean
it
added to the
begins. After
a term used frequently in serial data communications but
is
misunderstood.
often taken to
bits are
know where each word ends and
what
known
is
as a "parity bit" to the regular data bits
types of parity are used. If
the "Is" transmitted, including the parity
odd
bit, will
parity
is
sum of
used, the
be odd. For example,
the
if
data word contains three "Is", the parity bit will be zero. If four "Is" are in the data word, a "1" would be added by the transmitter so that the
of "Is" transmitted
The same
odd.
is
number
A
principle applies to even parity.
"1"
or "0" will be added in the parity bit to make the sum of bits transmitted an even number. The receiver, in both cases, will check to make sure that an odd
number of "l"s has been "l"s
if
even parity
is
received
if
odd
parity
is
used or an even number of
used. It should be pointed out that
within the transmitted word,
it
will not
if
two
bits
change
be detected by the parity detection
circuit. Only when one bit is lost during transmission will the error be detected and an error message presented. The role of start, stop, and parity bits is graphically displayed in Fig. 9.23. The relationship of the baud rate, the word rate, and the number of bits transmitted per second is shown below:
Baud Time
Word Baud
rate
=
1
/bit time
=
1/9.09 msec
to transmit one character rate
=
l/.l sec
rate of 110
= =
=
word
=
=110 (11 bits)
baud
X
(9.09 msec/bit)
=
.1
sec
10 characters/sec
(10 characters/sec)
X
(8 bits/character)
80 bits/sec (including parity)
Notice that the baud rate and the number of data bits transmitted per second are not the same. The baud rate of 1 10 includes the start and stop bits,
whereas the rate of 80 bits per second includes only information parity). In Fig. 9.23, a seven-bit
bits (including
ASCII word was transmitted. With the ACIA,
M6800 Microcomputer Family HO BAUD
187
— t — t — t-
SERIAL DATA TIMING FOR ASCII r
r I
II' i
i
!
i
!
X 00 START BIT—•>
-
BIT TIME (9.09 ms)
04
03
02
01
I
06
05
7 DATA BITS
•
PARITY BIT
•
STOP BITS ONE CHARACTER
Role of stop,
Fig. 9.23
WORDand
start,
parity bits
number of data bits (seven or eight), odd bits (one or two). Table 9.6 gives bit number of stop even parity, and the or data bits/sec for various baud rates. and characters/sec, time, character time,
several options are available as to the
Table 9.6 Baud Rate Data
Baud Bit
rate
time(msec)
110
150
300
1200
9.09
6.66
3.33
.833
.0092 sec
0.73 sec
.0366 sec
Characters/ sec
10
13.7
27.32
108.7
Data
80
110
218.6
870
'Character time bits/ sec
Assume
sec
.1
one start
bit,
eight data bits (including parity), and two stop bits, or
eleven bits per character.
Characters/sec
= = =
Data bits/sec
=Bx
Bit
time
Character time
To send and two stop
the
bits,
ASCII
1
/baud rate
number
(total 1
of bits in word)
x
(bit
time)
/character time
characters/sec
X (58
character
the pulse train
16)
would be
as
with one start
shown
bit,
even parity,
in Fig. 9.24.
h
-I
NEXT CHARACTER
/
DO
Dl
D2
D3
D5
04
06
4
t_±
START BIT
2 STOP BITS •
X«=58ig«l
I
I
t
t— DO
I
Dl
02 03
04 D5
06 Fig. 9.24 Pulse train
PARITY BIT
Basic Microprocessors and the 6800
188
Bit Synchronization
As
digital signals are transmitted
over a single
read erroneous results because of the noise on the
line.
line, it is
possible to
To minimize the chance
of such error, a sampling technique
is used to determine whether the start bit has been proved valid, each bit in the character word is sampled at approximately the center of the bit. is
valid. After
it
^ NOISE
NOISE
BIT
I
1
1
BIT 2
BIT 3
START BIT Fig. 9.25
Reading
If the receiving circuit
noise pulse
is
presence of noise pulse
start bit in
present (Fig. 9.25),
were to read the value of the start bit while a it would determine that the start bit is invalid.
Likewise, if a reading of bits 2 and 3 were taken during a noise pulse, it would read a "0" for bit 2 and a "1" for bit 3, neither of which would be correct.
The erroneous reading of
bits 2
detection circuit since the total
and
3
would not be detected by the
number of "Is" remains
parity
the same.
A method of minimizing the chance for an erroneous reading is to sample the start bit several times to determine if it is valid and then to sample each bit thereafter with a short pulse at approximately the center of the bit. Sampling at approximately the center of the bit minimizes the chance of error would have to be present at precisely the point where the sampling occurs. This sampling is accomplished by adding an external clock since the noise pulse
signal.
Clock frequencies of
The higher the clock
16, 32,
and 64 times the baud
rate are often used.
frequency, the less the chance for a false reading.
MC6850 ACIA, which
The
frequency of
1,
16,
be discussed shortly, can accommodate a clock and 64 times the baud rate. These frequencies are referred
to as the
1,
-r-
16,
-h-
will
and
-r-
64 modes.
To illustrate what all this really means, assume that the partial character being received is
preceded by the normal start bit. If a clock rate of 16 times baud rate (-=-16 mode) is being used, as shown in Fig. 9.26, the receiver, upon detection of the mark-to-space transition, will start its sampling on the rising edge of the external clock. If the signal remains low for nine separate samplings (in the -f- 16 mode), the bit is assumed to be a valid start bit and the
is
shifted into the
ACIA
shift register
during the falling edge of the internal
clock. After every sixteenth pulse thereafter
a reading will be
If a clock rate of 64 times the baud rate were used (-r- 64 mode), the would be determined valid after a sampling of 33 readings. The data would be sampled every 64 pulses from the center of the start bit.
start bit
bits
from the center of the start bit, respective bit is a "1" or "0".
made to determine whether that
189
M6800 Microcomputer Family BITO START BIT
/,
L_
\ 9 READINGS
I
16
»*
«
READINGS
Fig. 9.26
-h-
mode
If the start bit in Fig. 9.26 is
as
shown
sampling
expanded, the sampling would appear on the start bit. Since it did not
in Fig. 9.27. Notice the noise pulse
occur during the sampling period,
determined to be
MARK
it
goes by undetected, and the start bit
is
valid.
/
~L
END OF START BIT
NOISE
SPACE
t rnal
clo ck (-H6)
njxnjTJTJTJTJT_n_ru-
TTTTtTTTT SAMPLE 9 START BIT SHIFTED TO THE s> ACIA SHIFT REGISTER IF IT HAS BEEN DETERMINED TO BE VALID
INTERNAL CLOCK
Sampling with expanded
Fig. 9.27
start bit
The same argument applies to each data bit. Notice in Fig. 9.28 that on the sixteenth pulse from the center of the start bit, a sampling takes place, yet, despite the noise on the line, the correct data is shifted into the ACIA since the noise does not occur during the sampling period.
CENTER OF FIRST BIT
CENTER OF START BIT
~U
BITO
-UTJTJTJTJTJTJTJTJTJTJTJT^ f
t
t
t
f
f
f
f
f
t
t
t
t
t
SAMPLE
16,
t
t
LEVEL OF BIT IS DETERMINED TO BE A "l" AT THIS PRECISE POINT.
Fig. 9.28
Sampling at sixteenth pulse
Basic Microprocessors and the 6800
190
ACIA
Description of the
The MC6850 Asynchronous Communications Interface Adapter (ACIA) is an N-MOS device housed in a 24-pin package that is used as a means of receiving and transmitting as many as eight bits of data in a serial format (Fig. 9.29). The ACIA communicates (transmits/receives data) with the MPU via an eight-bit bidirectional data just as RAMs, ROMs, and PIAs do. The ACIA has four registers that may be addressed by the MPU. The and the Receiver Data Register (RDR) are "read only" meaning that the MPU cannot write into them. The Transmit Data Register (TDR) and the Control Register (CR) are "write only" registers, meaning that the MPU cannot read them. Status Register (SR)
registers,
In addi tion to these four registers, the ACIA has three chip select lines (CSO, CS1, CS2), one register select line (RS), one interrupt request line (IRQ), one enable line (E), one read/w rite li ne (R/W), and seven data and data control lines
(RXC, TXC, DCD, RTS, RXD, TXD, and CTS). ACIA
MC6850
• 24
FROM SYSTEM GR0UN0
6ND
FROM PERIPHERAL
RX DATA
FROM EXTERNAL CLOCK
,22
DO
20
RTS
MODEM OR PERIPHERAL
IRQ
Ji-^ Ji~^
CSO
il—
TX DATA
TO MPU IRQ LINE
FROM MPU ADDRESS
FROM MODEM OR PERIPHERAL
TX CLOCK
TO MODEM OR PERIPHERAL TO
,23
DCD
RX CLOCK
FROM EXTERNAL CLOCK
FROM MODEM OR PERIPHERAL
CTS
«
CS2
16
TO/FROM MPU
>D0-D7 DATA LINES
»
-<
LINES
CSI
RS
FROM TTL
E
+5V
FROM SYSTEM POWER
R/W
Fig. 9.29
2 CLOCK
FROM MPU R/W LINE
ACIA package
MPU Interface Lines Data Lines (D0-D7)
Bidirectional lines
The
eight bidirectional data
ACIA and the MPU. The MPU and to the outside world through the ACIA via
permit transfer of data to and from the
receives
and sends data from
these eight data lines.
The data bus output
remain in the high impedance
ACIA
(off) state
drivers are three-state devices that
except
when
the
MPU performs an
read operation.
Chip Select Lines (CSO, CSI, and CS2) It is through these lines, which are tied to the address lines of the MPU, that a particular ACIA is
M6800 Microcomputer Family
191
For this selection, the CSO and CS1 lines 'must be high and the CS2 must be low. After the chip selects have been addressed, they must selected (addressed).
be held in that state for the duration of the
MPU
timing signal supplied by the
The enable
Enable Line (E) compatible input from the
to the
E
enable pulse, which
Read/ Write Line (R/W) ance, TTL-compatible input that
pulse
is
a high-impedance,
is
TTL-
The read/write
is
usually the
line is
TTL
a high-imped-
used to control the direction of data flow
between the ACIA's eight-bit parallel data bus and the
MPU. When
read/
(MPU read), the ACIA output driver is turned on, and a selected read by the MPU. When the read/write line is low (MPU write),
high
is
register
the
the only
MPU that enables the ACIA input or output buffers
and that clocks data to and from the ACIA. This input 2 signal from the clock.
write
is
ACIA.
is
ACIA
output driver
is
turned
off,
MPU
and the
writes into a selected
register.
Register Select (RS) The register select line is a high-impedance, TTL-compatible input from the MPU that is used to select, in conjunction
with the read/write
line, either
line
from the
the transmit/receiver data register or the
ACIA
control/status register in the
(Fig. 9.30). It
must be
tied to
an address
MPU. A high or RS selects transmit/receive data registers; a low
selects control/status registers.
Modem
Control Lines
Serial data to be transmitted over telephone lines must be sent to a that prepares the signal for transmission (Fig. 9.31). Three signals
modem
between the
ACIA
and the
Modem
Clear to Send (CTS) provides via the
permit a limited control of the
latter.
This high-impedance TTL-compatible input
automatic control of the transmitting end of the communications link output by inhibiting the Transmit Data
modem CTS-signal active-low
Register
Empty (TDRE)
status bit. If this line
is
not used,
it
should be tied
to system ground.
Request
to
Send (RTS)
This
ACIA
output enables the
MPU to
modem via the data bus. The RTS output corresponds to the state of control register bits 5 and 6. When CR6 equals "0" or both CR5 and CR6 equal "1", the RTS output is low ( the active state). This output can
control a peripheral or
Data Termina l Ready (DTR) on the 6860 modem. Data Carrier Detect (DCD) This high-impedance, TTL-compatible input provides automatic control of the receiving end of a communication link by means of the modem Data Carrier Detect (DCD) output. The DCD input inhibits and initializes the receiver section of the ACIA when high. A also be used for the
low-to-high transition of the
DCD
line initiates
indicate that a loss carrier has occurred
when
(RIE)
it
bit is set. If this line is
not used,
an interrupt to the
MPU to
the Receiver Interrupt Enable
should be tied to system ground.
Basic Microprocessors and the 6800
192
ACIA
GNO
~l
TRANSMIT DATA REGISTER (TOR) SERIAL DATA OUT
WRITE ONLY
PWR
TXO
(+5)
|
BUS ORIVERS
FROM MPU DATA
STATUS REGISTER
LINES (PARALLEL TO SERIAL CONVERTER)
7
6
5
4
IRQ
PE
OVRN
FE
3
CTS
(SR)
2
1
DCD TDRE RDRF
READONLY
CONTROL REGISTER 7
TO MPU DATA LINES (SERIAL TO
6
S
|
•I
1
2
WS
TC
RIE
3l
(1:r)
PARALLEL CONVERTER)
COS
WRITE
ONLY
RXD
SERIAL OATA IN
L_IRQ
RECEIVE DATA REGISTER (RDR) RS R/W E
r RECEIVE
INTERRUPT TO
CLOCK
MPU TRANSMIT CLOCK
T"T
,
CTS
I
CLEAR TO SEND
WRITE
(A„)
FROM REGISTFR SELE :t
MPU
CS1
CS2
DCD
n [TT 1
•
SIGNAL
CHIP SELECT
FROM MODEM
FROM MPU ADDRESS LINES
FRON MPU ADOF ess LINE
REQUEST TO SEND TO
»
MODEM DAI A CAF RIER DET ECT FRO M M0()EM
Fig. 9.30 Register select line
MPU SYSTEM
o
RECEIVE
MODEM
ACIA
MC6850
Fig. 9.31
MC6860
TRANSMIT
__
.
Modem
RTS
,
ENABLE
READ OR
CSO
.
__
control line
m
|
M6800 Microcomputer Family
Serial
193
Data Lines
The ACIA has two lines for transfer of data. The Transmit Data (TX DATA) line is used to send, and the Receive Data (RX DATA) line to receive, data from a peripheral. Before transferring data, the ACIA will add the start bit automatically.
The number of stop bits and odd or even parity will also be word per instructions via bits 2, 3, and 4 of the control
specified in the data
As
register.
data
is
received over the receive data
line,
the
ACIA
will use the
number of "l"s received, and it will data word before converting the data bits
parity bit to check the accuracy of the strip the start
and stop
bits
from the
to a parallel format for transfer to the
Receive Data
(RX DATA)
MPU The
over the data bus.
receive data line
ance TTL-compatible input through which data Internal synchronization for detection of data
is
is
possible with clock rates of
16 or 64 times the bit rate. Data rates in the range of
second are possible with external synchronization
Transmit Data
(TX DA TA)
to transfer data in a serial format to
(in the
to 500,000 bits per -?-
1
mode).
The transmit data output line is used a modem or peripheral. Data rates in the
to 500,000 bits per second are possible with external synchronization
range of (in the
a high-imped-
is
received in a serial format.
-=-
1
mode).
External Clock Inputs Separate high-impedance, TTL-compatible inputs are provided for clocking of transmitted and received data. Clock frequencies of
times the data rate
may be The
or 64
The transmit clock input is used for clock-
Transmit Clock (TXC) ing transmitted data.
16,
1,
selected.
transmitter initiates data on the negative transition
of the clock. Receive Clock
The
(RXC)
chronization of received data. transition of the clock. (In the
The -r-
1
receive clock input
is
used for syn-
on the positive mode, the clock and data must be synchroreceiver strobes the data
nized externally.)
Transmit Data Register (TDR) The format) until
it is
on the negative
transferred.
The data is written into the transmit data register
transition of the enable (E) signal after the
CS2
lines
and the RS
ACIA line is
has been a "1" and
R/W line is a "0". Writing data into the transmit data register causes the
Transmit Data Register Empty ("0"). After the is
is
MPU (converted from parallel format to serial
addressed through the CS0, CS1, and the
ACIA,
transmit data register, an eight-bit register within the
used to hold the data from the
(TDRE)
bit in the status register to
go low
TDRE bit goes low, data will be transmitted. If the transmitter
idling (no character being transmitted), then the transmission will occur
Basic Microprocessors and the 6800
194
within one bit time of the trailing edge of the write is
being transmitted,
will
it
command.
If previous data
be transferred upon completion of the previous
transmission. After the data has been transmitted, the to a "1", indicating that the is empty.
TDRE will be changed
TDR
Receive Data Register
The the data that
(RDR) an eight-bit register within the ACIA, holds from the modem or peripheral to the ACIA. After
receive data register, is
transferred
the receive data register
is full,
the data
the parallel data bus, and the Receive
is
ready for transfer to the
MPU over
Data Register Full (RDRF)
bit in the
go high ("1"). indicating that the register is full. The RDRF bit's going high causes the IRQ bit of the status register to go high as well and to remain high until the data is read into the by addressing the ACIA through the CSO, CS1, and CS2 lines and by setting the RS and R/W lines status register will
MPU
to a "1". After the data
is read by the a "0", but the data will remain in the
MPU, RDR.
RDRF bit
will
be reset to
an eight-bit register within the
ACIA that
the
Status Register (SR)
The
Status Register (SR)
is
maintains the current condition of internal only register in that the
MPU cannot store any data in
to check the status of certain events. selected through the CSO, CS1, line being held
ACIA activities (Fig.
To
read
and the CS2
low ("0") and the
R/W
its
7
6
5
4
3
PE
OVRN
FE
CTS
ACIA
must be
with the register select (RS)
high ("1").
line
IRQ
A read MPU
used by the
contents, the
lines,
STATUS REGISTERS
it, it is
9.32).
(SR)
2
1
DCD TDRE RDRF
Fig. 9.32 Status register
Bit (^Receiver Data Register Full "I":
(a) Indicates that the receiver
(b)
The IRQ
data "0":
(RDRF)
is
data register
bit also gets set to a
read by the
set until the
MPU.
(a) Indicates that the contents
been read into the
is full.
"1" and remains
of the receiver data register have
MPU. The data is retained in the register.
DCD line goes high, and the RDRF bit is clamped at "0", indicating that the contents of the RDR are not current. (c) A master reset condition also forces the RDRF bit to a "0".
(b) If there is a loss of carrier, the
195
M6800 Microcomputer Family Bit
1— Transmit Data "1"
Empty (TDRE)
Register
(a) Indicates that the contents of the transmit data register
:
been transferred and that the register
is
now
have
ready for more
data, (b)
The IRQ
a "1" and remains set until a
bit also gets set to
write operation to the transmit data register.
"0":
(a) Indicates that the transmit
(b)
a "1"
When
(bit 3)
of the
SR
2—Data
of the
(a) Indicates that there is
(b)
is full.
pin and causes the
TDRE
will
CTS
it is
not
be clamped to a "0".
(DCD)
Carrier Detect
"1":
register
CTS
to get set to a "1" to indicate that
clear to send, bit
Bit
d ata
present on the
is
The IRQ
no
bit also gets set
from the modem. and remains set until the
carrier
MPU
reads the status register and the receiver data register or until
a master reset occurs. (c)
This causes the
RDRF bit to be clamped at a "0", inhibiting RDRF. modem is
further interrupts from
"0":
Bit
(a)
The
3— Clear to Send "1":
carrier
present.
(CTS)
Indicates, via the high clear-to-send line
the latter
"0":
from the
is
Indicates, via the
the
modem
from the modem, that
not ready for data.
is
low clear-to-send
line
from the modem, that
ready for data.
—Framing Error (FE)
Bit 4
"1":
Indicates that the received character
the start
of the
and stop
first
bit.
stop bit
This error
and
is
is
improperly framed by
detected by the absence
indicates a synchronization error,
faulty transmission, or a break condition. set
The
error flag
is
or reset during the receiver data transfer time and
is
therefore present throughout the time that the associated
character "0":
Bit
5—Receiver Overrun "1":
is
available.
Indicates that the received character
is
properly framed.
(OVRN)
Indicates that one or
more characters
in the
data stream has
a character or a number of characters has been received, but not read, from the Receiver Data Register (RDR) prior to subsequent characters being received. The
been
lost, that is,
Basic Microprocessors and the 6800
196
overrun condition begins at the midpoint of the last bit of the second character received in succession without a read of the having occurred. The overrun does not occur in the
RDR
status register until the valid character prior to overrun has
been read. Character synchronization
The overrun
the overrun condition.
the reading of data from the
is
maintained during
error flag
RDR. Overrun
is
is
reset after
also reset
by
the master reset. '0":
Bit
No
receiver overruns have occurred.
6—Parity Error "1":
(PE)
Indicates that the
number of highs
(" 1 "s) in the character does
not agree with the preselected odd or even parity. tion,
odd
By definiwhen the total number of "l"s, inis odd. The parity error indication will
parity occurs
cluding the parity
bit,
be present as long as the data character parity
selected, then
is
is
in the
RDR.
If no
both the transmitter parity generator
output and the receiver parity check results are inhibited. "0":
Bit
No
parity error occurred.
7—Interrupt Request "1":
(IRQ)
Indicates that there
IRQ
is
an interrupt present that has caused the
output line to go low. The interrupt will be cleared by
a read operation to the
RDR
or a write operation to the
TDR. "0":
Indicates
no interrupt
present.
Control Register (CR)
The Control
Register (CR), an eight-bit register within the
ACIA,
is
MPU to control the transmitting and receiving of serial data (Fig. It is a write only register since the MPU cannot read To write into
used by the 9.33).
it.
ACIA
must be selected via CS0, CS1, and CS2, and both the RS and the R/W line must be low ("0"). it,
the
CONTROL REGISTER 7
R 1
6
5
4
3
(CR)
2
Word
Counter
Control
Select
Divide
E
*
1
Transmitter
—
Rece ver
Int errupt
E nable
Fig. 9.33 Control register
line
197
M6800 Microcomputer Family
and
Bits
1— Counter Divide Select Bits
(CDS)
These two bits determine the divide ratios utilized in both the transmitter and receiver sections of the ACIA. They are also used for master reset of the ACIA, which clears the status register (except for external conditions on CTS and DCD) and initializes both the receiver and the transmitter. Master reset
the
does not affect other control register
ACIA
bits.
After a power failure or restart,
reset before setting the clock divide ratio. Bit patterns for
must be
the various functions are
shown below.
cm
CRO
Function -4-5-
1
-=- 64 Master reset
1 1
1
4— Word Select Bits
Bits 2,
3,
of stop
bits,
1
16
(WS)
The programmer has the option of selecting the word and type of parity by using the proper
bit pattern
length,
number
from the chart
below.
34
B2
B3
Word Length
1 1 1
1 1
1
1 1
1
1
1
Bits 5
and
1
6— Transmitter
The
Parity
+
Stop Bits
7
Even
7
Odd
2 2
7
Even
1
7
Odd
8 8 8 8
None None
2
Even
1
Odd
1
1
1
Control Bits (TC)
status of bits 5
and 6 of the control
register provide for control
of the interrupt from t he Transmit Data Register Empty (TDRE) condition, the Request To Send (RTS) output, and the transmission of a break level (space), as
shown below.
198
Basic Microprocessors and the 6800
CR6
CR5
Function
The RTS This
is
pin
is
low and Transmit
the code used
when
Interrupts are inhibited.
requesting that the
communications channel be set up. data
It
is
not clear to send
yet.
The RTS
pin
been set
up. Therefore, this
via the
is
TRDE
low and the communications channel has code is used to generate IRQs the Status Register.
bit in
The RTS pin is high and transmit interrupts are This code can be used to "knock down" the
inhibited.
communications channel.
The RTS
pin is low (keep up communications channel) and a break signal (low level on transmit data out line) is transmitted. This is used to interrupt the remote system.
Bit
7—Receiver Interrupt Enable "1":
(RIE)
Enables interrupts caused by:
(RDRF)
(a)
Receiver Data Register Full
(b)
A low-to-high transition on the data carrier detect signal
going high.
line.
"0":
Inhibits interrupts caused
by
RDRF or by
data carrier.
FROM POLLING ROUTINE (MAIN PROGRAM)
RTS (RETURN TO MAIN PROGRAM)
Fig. 9.34 Flowchart of transmit
sequence
the loss of receive
199
M6800 Microcomputer Family
Power On is applied, the ACIA master reset should be program, which stores a "1" in CRO and CR1 of the ACIA control register. After master reset, the variable clock divide ratio bits, the transmitter interrupt bits, and the receiver interrupt bit of the ACIA
After the system power
set
by the
initialization
control register should be set by the initialization program.
Transmit Sequence The
flowchart in Fig. 9.34 illustrates a typical sequence followed in
transmission of serial data (for an example of
ACIA programs, see Chap.
1 1).
Receive Sequence
The
flowchart in Fig. 9.35 illustrates a typical sequence followed in FROM POLLING ROUTINE (MAIN PROGRAM!
NO
RETURN TO ^ *"
MAIN PROGRAM
YES
^ FRAMING ERROR ROUTINE
YES
^
OVERRUN ERROR ROUTINE
YES
*"
PARITY ERROR
ROUTINE
RTS (RETURN TO MAIN PROGRAM)
Fig. 9.35 Flowchart of receive
sequence
200
Basic Microprocessors and the 6800
the receiving of serial data by the
ACIA (for an example of an ACIA program,
see Chap; 11).
Problems Microprocessor 1.
How many
does each of the following registers contain?
bits
(a)
A
(d)
X
(b)
B
(e)
PC
(c)
CC
(0 SP
2.
How many
3.
Running
wide
bits
at the
the data bus?
is
maximum
The address bus?
rated clock frequency,
what
is
the time required to
execute the shortest instructions on the 6800? 4.
Where does
MPU get the program starting address upon first starting up?
the
program counter (sets to zero) and therefore always program at 0000. goes to the program starting address set up by the front panel
(a) It clears the
starts a
(b) It
switches of the microcomputer. (c) It fetches
bytes in
an address for the program
memory corresponding
FFFE
to
start
and
from the two highest on the address
FFFF
bus. (d) It always starts executing a
FFFF. (e) The
MPU
inherently
program
knows where
FFFE
and
program and
will
at addresses
to start a
automatically set the program counter to the proper address without being directed. 5.
What
is
the state (0 or 1) of each of the following condition code register bits
after instruction
ber FF)
is
(a) Bit
6. If
7.
8.
LDA A #$FF (load accumulator A with hexadecimal num-
executed?
N
(b) Bit
Z
(c) Bit
V
the interrupt bit (I bit)
is set
to a "1"
and a
WAI instruction is encountered,
how can the MPU exit from this situation? Assume the address of the stack pointer is hex the
MPU
If a
system has two PIAs and two ACIAs,
registers
be stored in
if
8B.
What
address will each of
an interrupt occurs?
how
does the
MPU
know which
device causes an interrupt? 9.
10.
11. 12.
How many locations can be addressed by the MPU in hex? In decimal? Which pin can halt the processor for an indefinite amount of time? Which interrupt pin can be masked? Which pin indicates that a number on the address bus is an arithmetic operand?
201
M6800 Microcomputer Family 13. 14. 15.
Which pin can halt the microprocessor for a maximum of 4.5 jmsec? Which pin refreshes the data bus drivers? Which pin indicates that the address bus and the data bus have gone three-state during a halt?
16.
Which output
pins cannot be three-stated?
17.
Determine the
state of the condition
ABA A = 1111 1111 B = 0000 0001
code
bits after the following operations:
(a)
DECA A = 0000 0000
N =
Z =
H = V =
Z =
H = V =
C =
H =
N = C =
A + B=
C =
(b)
(c)
A=
LDA A #01
A= z = (d)
INC
A =
V =
A
0111 1111
A=
What is
N = C =
H = z =
18.
N =
V =
the value of the program counter (PC) after completion of the follow-
ing interrupt sequences:
(a)
After an
IRQ
an After an
NMI
(b) After (c)
FFFF FFFE FFFD FFFC FFFB FFFA FFF9 FFF8
SWI
(d) After restart
F
E
8 F
C
F 8 F
D D
Memories 19.
How many
Which
MCM6830 ROM?
(a)
128
(d) 1024
(b)
256 512
(e)
(c)
20.
bytes in a
pin(s) (a)
(b) (c)
on the
MCM6810
Data bus Read/Write Address bus
and
4096
MCM6830
is
(are) three-state?
(d)
Chip
(e)
All of the above
selects
.
Basic Microprocessors and the 6800
202 21.
Why
22.
What and
23. 24.
MCM6830
doesn't the
ROM
have a R/W pin? and negative chip
are the purposes of the positive
selects
on the
ROMs
RAMs?
What are the What power
contents of the last eight
ROM
locations in any system?
RAM
MCM6810
supply voltages are required for the
and
MCM6830 ROM?
25.
What
is
-5
(a)
+5, -12
(d)
+5,
(b)
+5
(e)
None
(c)
+15, +5, -15
MCM6810 RAM?
the organization of the (a)
1024
(b)
512
(c)
4K
of the above
X 1 X 4
(d) 128 bytes (128 (e)
bytes (4096
X
X
1024 bytes (1024
8)
X
8)
8)
PIA 26. 27. 28. 29.
How many How many How many
registers are in the
PIA?
register select pins are in the total lines
PIA?
can we have to the "outside world" on a PIA?
Although the A side and B side of the PIA are identical in most respects, there are two differences. One difference is in the internal I/O construction; the other difference
is
(a)
that
The
A side can be either input or output
whereas the (c)
The B The A
(d)
Both
(b)
A
B
on the eight data
lines,
side can only be output.
side has
no control
side does not
register.
have the
"bit following"
mode
capability.
A and B side interrupts are reset as a result of a read of the
side data register, whereas only the
a result of a read of the
B
B
side interrupts are reset as
side data register.
(e) Reading from the A side Or writing to the B side causes the handshake or pulse modes on the respective side if it is programmed for one of those modes.
PIA
A
30.
Can we have
31
How does the microprocessor know whether it is the A side or the B side which
three inputs
and
five
outputs on the
side?
IRQ lines from both sides are normally tied together.) 32. How can six registers be addressed with only two register selects? 33. After restart, what steps must be taken before the PIAs can be used? causes an interrupt? (Recall that both the
34. In
each of the following diagrams,
that
match the I/O
lines.
fill
in the bits of the data direction registers
203
M6800 Microcomputer Family PAO PA1
DDRA
PA2 PA3 PA4 PA5 PA6 PA7
PAO PA1
DDRA
PA2 PA3 PA4 PAS PA6 PA7
MC6821 PIA
PBO PB1
DDRB
PB2 PB3 PB4 PB5 PB6 PB7
MC6821 PIA
PBO PB1
DDRB
PB2 PB3 PB4 PB5 PB6 PB7
(a)
(b)
PAO PA1
DDRA
PA2 PA3 PA4 PA5 PA6 PA7
PAO PA1
DDRA
PA2 PA3 PA4 PA5 PA6 PA7
MC6821 PIA
PBO PB1
DDRB
PB2 PB3 PB4 PB5 PB6 PB7
MC6821 PIA
PBO PB1
DDRB
PB2 PB3 PB4 PB5 PB6 PB7
(c)
(d)
Basic Microprocessors and the 6800
204
35. In the following diagrams,
fill
in the bits required to
program the interrupt
control lines as specified.
CA1
CA1
CA2
CA2
CRA
lolol
1
1
CRA ll
1
I
I
lolol
I
CRB
lolol
1
1
I
|1
I
I
I
I
I
I
CRB 1
I
I
I
lolol
I
I
1
CB1
MC6821 PIA
(a)
CB1
CB2
—Negative edge, masked — edge, unmasked CB1 — edge, masked CB2— Negative edge, unmasked
CA1 CA2
CB2
MC6821 PIA (b)
Positive
Positive
—Positive edge, masked —Pulse mode CB1 —Positive edge, unmasked CB2—Zero
CA1 CA2
CA1
CA1
CA2
CA2
CRA
CRA
lolol
I
I
|1
I
I
I
lolol
I
I
I
1
I
|
I
lolol
|
MC6821 PIA
CB2
—Positive edge, unmasked —One CB1 —Negative edge, masked CB2— Handshake mode
CA1 CA2
36. In the following diagrams,
and B shown
I
1
|
I
I
I
I
MC6821 PIA
(d)
CB2
—Negative edge, unmasked —Handshake mode CB1 — Negative edge, unmasked CB2—Pulse mode
CA1 CA2
determine the data that would be read from the A shown on the I/O lines and with the data
sides with the logic levels in the registers.
|
CB1
CB1
(c)
1
CRB
CRB
lolol
I
1
205
M6800 Microcomputer Family
L = Low
11111111
00000000 00000000
A
side data
B
side data
A
side data
B
side data
logic level
PAO
PA1
PA1
PA2 PA3 PA4 PA5 PA6 PA7
PA2 PA3 PA4 PA5 PA6 PA7 00001
PDRA DDRA PDRB DDRB
1 1
00000000 01110111 00001
1 1
PB0
PBO
PB1
PB1
PB2 PB3 PB4 PB5 PB6 PB7
PB2 PB3 PB4 PB5 PB6 PB7 (b)
A
side data
B
side data
= =
PAO
PAO
PA1
PA1
PA2 PA3 PA4 PA5 PA6 PA7
PA2 PA3 PA4 PA5 PA6 PA7
PDRA DDRA PDRB DDRB
= =
High
PA0
= =
00000001 11101101 11111010 01010011
(c)
H =
PDRA DDRA PDRB DDRB
00000000
(a)
logic level
11011010 00110010 10000001
01100110
PDRA DDRA PDRB DDRB
PBO
PBO
PB1
PB1
PB2 PB3 PB4 PB5 PB6 PB7
PB2 PB3 PB4 PB5 PB6 PB7 (d)
A
side data
B
side data
206 37.
Basic Microprocessors and the 6800
Each PIA shown
in the following
Determine the control
line that
CRA
M h
I
1
lolo
M h h
diagrams has interrupted the processor.
caused the interrupt in each case.
-
CA1
«-
CA2
CRA
M
lol
lo io
1
1
MC6821
PIA
PIA
CRB
CRB I
1
I
lol
1
I
«-
CB1
-
CB2
1
lo
I
1
I
I
(a)
I
o|o|
1
o
1
1
1
1
I
o
CRA
CA2 I
«-
CB1
-
CB2
CA1
CA1
I
CA2
(b)
CRA 1
CA1
«-
h hhl
li
MC6821
|o |o |0 |0
-
TToTo"
1
|0
I
1
|0 |0
CA2 I
MC6821
MC6821
PIA
PIA
CRB
CRB
iiiiohnniTTo"
1
|0
M
I
1I0I1I0I1I1I1I0I
CB1
CB1
CB2
CB2 (d)
(C)
ACIA 38.
During
serial
transmission at 300 baud,
mitted each second
how many
information bits are trans-
each character has seven information bits with no parity
if
bit?
39. If the
ACIA
control register
word
select bits contain a
external clock pulses are needed in the 16
and the information 40.
What
does (a)
(b) (c)
(d)
mode
hex
5,
how many
to transfer both the start bit
bits?
ASCII stand
for?
American Standard Code for Information Interchange A Standard Communication Version 2 Asynchronous Standard Code Version 2 Asynchronous Serial Code in Industry
— —
207
M6800 Microcomputer Family 41.
Can code
42. 43. 44. 45.
the
MC6850 ACIA
be used to transmit eight-bit data other than ASCII
serially?
How many registers in the ACIA are accessible from the data bus? How are these registers selected with only one register select line? What is the first thing that must be done Which of the following bits in the status (Choose
an interrupt?
RDRF (Receive Data Register Full) TDRE (Transmit Data Register Empty) PCD (Data Carrier Detect)
(b) (c)
(e)
CTS (Clear To Send) FE (Framing Error)
(f)
OVRN
(d)
(g)
we were
ACIA?
that apply.)
all
(a)
46. If
to initialize the
register could cause
PE
(Receiver
OverRuN)
(Parity Error)
using odd parity, give the parity bit (0 or
1) for
the following data
bits:
(b)
1101100 0000000
(c)
1100001
(a)
47.
What
and 2 only) should we write into the control from a standard 10-character/sec. model 33 Teletype
bit pattern (for bits 4, 3,
register to send/receive
machine? (Assume even
parity.)
System 48.
Assume, as part of your system, that you have two MCM68 10 RAMs that start bottom of memory. Your program is to check the first five bytes location is an odd number, of the second RAM. If the contents of that invert each bit and store this result back in that location; if an even number, clear that location. Generate a flowchart and write a program to accomplish the above task. The program is to start at hex location 2000. at the very
RAM
RAM
RAM
10
System Configuration In Chap. cussed.
9,
each of the basic devices in the
M6800
family was dis-
How do we wire all these devices together to form a system? How are
addresses determined? Such questions will be answered in this chapter.
The
connection of each pin on each device will be shown.
To three
illustrate as
many
MCM6810 RAMs,
principles as possible, a system consisting of
three
MCM6830 ROMs,
MC6850 ACIA, and one-MC6800
mum
possible
number of
three
MC6821
MPU will be configured. This may
devices which
PIAs, one
is
the maxi-
be tied to the data bus without
additional buffering.
The RAMs will be located at consecutive addresses starting at address
RAMs are used for reading and storing data frequently, the 256 bytes of the RAMs can be addressed in the direct mode, that is, with two rather than three bytes of memory. (STA A $75 takes two bytes of memory whereas STA A $7505 takes three bytes of memory.) In our sample system, the addresses will be 0000 to 017F.
0000. Since the first
RAM
The
ROMs will be located
address in the system assigned to
in consecutive addresses
the contents of the last eight addresses in the last
of the IRQ, SWI,
with the highest
ROM. This arrangement is necessary because
NMI, and RESTART
FFFE and FFFF
ROM contain the addresses restart, the MPU
programs. During
on the address bus
sequentially, thus caus-
ing the contents of these locations to be placed in the
program counter. Since
places addresses
the program counter
now
contains the address of the restart program, the
MPU is ready to start program execution. In the example we will be showing, the
ROMs
will
be located at address 8400 to 8FFF.
The PIAs and ACIAs will be
located at addresses between the highest
RAM address and the lowest ROM address in the system. PIA # PIA #2
1
will
be at
4008 through 400B, and PIA #3 at addresses 4010 through 4013. As you have probably noticed, these addresses are not consecutive. There is no reason why they need be. However, because of the chip selects available, it is not possible, normally, to have all addresses 4004 through 4007,
three
PIAs
at addresses
at consecutive addresses. This fact will
become obvious when we
review the system layout worksheet later on. The ACIA will be at addresses 4020 and 4021. 208
209
System Configuration
ALL LIKE DATA LINES ARE TIED TOGETHER
DO D1
D2 D3 D4 D5 D6 D7
33
2
1 U
32^\
31^
30
5 fe f?
29"*
28^
27
'8 '9
26^
r
2
DO D1
A '5
D2 D3 D4 D5 D6 D7
'S 'a '9
r
s^
33
C 32 '31 '30 '29 '28 '27
,^
BUS"^^
r
26
r
2
f3
D1
'4
D2 D3 D4 D5 D6 D7
'5 '6 *7 '8 'S r
PIA
33
DO
(Z2
D1
D2 D3 D4 D5 D6 D7
'30 '29 '28 '27 '26
r
#2
'4 '5 '6 '7 '8 '9 r
2 'A
D2 D3 D4 D5 D6 D7
'a '9
—
t
DO D1
D2 D3 D4 D5 D6 D7
ACIA 22
'19 '18 '17 '16 '15 r
DO D1
D2 D3 D4 D5 D6 D7
Fig. 10.1
'31
D2 D3 D4 D5 D6 D7
u
21 C'20
33
f32
D1
'30 '29 '28 '27 '26 r
ROM #2
DO D1
D2 D3 D4 D5 D6 D7
#3
DO D1
D2 D3 D4 D5 D6 D7
^
ROM #1 2
D1
PIA
DO
J
(3
DO
-
#1
s^
RAM #3
DO
*
PIA
DATA
RAM #2
RAM #1
MPU
Data bus
ROM #3 2
(3
rA '5
'6 '7
'8 '9
DO D1
D2 D3 D4 D5 D6 D7
210
10.1
Basic Microprocessorsand the 6800
Data Bus All data lines of the same
MPU
is
and the
DO of all
tied to the
number
PIAs, the
DO from the DO of all ROMs,
are tied to each other.
DO of all RAMs,
the
DO of all ACIAs. The same is true of each of the remaining data lines.
See Fig. 10.1.
10.2
Read/Write Line
10.2).
Notice that there
All
stored in a
R/W
pins of each device in the system are tied together (Fig.
no
is
R/W
pin on the
ROMs.
Since data cannot be
ROM, a ROM must be addressed solely to obtain data (read only).
(NOTE: During
the three-state modes,
sure that nothing gets written into a so with a pull-up resistor on
VMA goes low, and we have to make
memory
location by accident.
R/W to insure a read state,
or, in
We can do
some
systems,
VMA may be connected to a chip select on the RAMs. Either way, protection is
adequate.)
READ/WRITE LINE
MPU
RAM
R/W
34
,6 Ii
4.7 K
ACIA
+ 5V
R/W
#\
RAM 16
R/W
#2
R/W
RAM 16
Jff
3
R/W
i
—WV-"
'
,
PIA#2
PIA#I 2I
13 ,
21
R/W
——— Fig. 10.2
R/W
PIA#3 21
R/W
i
Read/ write
line
10.3 Interrupt Line
IRQA
IRQB lines of each PIA normally should be tied IRQ input of the MPU. In our system, we shall assume that IRQB of PIA#3 will be used for a nonmaskable interrupt ( NMI). All remaining IRQA and IRQB will be tied together with the IRQ of the ACIA and connected to the IRQ input on the MPU. See Fig. 10.3. The
and
together and connected to the
10.4 Reset Line The RES input all
pin on the
MPU
PIAs. The signal applied to the reset
See Fig. 10.4.
should be tied to the
line will
RES
be from an external
pins
on
circuit.
211
System Configuration
+5V MPU
NMI
4
38
38
IROA 6 i
41
IRQB
PIA#3
»IA#2
»IA*M
£3K
IRQ
38
IROA
37
,3 IRQB
IROA IRQB
ACIA 7
IRQ
Fig. 10.3 Interrupt line
MPU
PIA*3
Fig. 10.4
VMA signal,
1.
is
when
high, indicates that a valid address
is
being
MPU.
There are two times when the address on the invalid (thus producing a low signal):
applied to the bus by the
address bus
line
Memory Address
10.5 Valid The
Reset
During some internal operations, the MPU allows invalid adon the bus because they are not used. Anytime the bus is three-stated (TSC high), it is floating and
dresses to appear 2.
therefore invalid.
VMA
is
used to prevent destruction of data in the system caused by
writing into a location inadvertently, or, in the case of a
reading a register and accidently erasing some interrupt
During condition state so that nothing
1
above, the
PIA
or
ACIA, by
flags.
MPU holds the R/W line in the read ANDing VMA and
can be written into any location. By
an address line that is tied to a chip select input on the PIAs and ACIAs, the PIAs and ACIAs are protected from an accidental read that would clear
212
Basic Microprocessors and the 6800
possible interrupt flags (Fig. 10.5).
The connection
if desired.
is
(NOTE:
VMA may be connected to ROM ROM
not absolutely necessary since data in
cannot be destroyed, but no harm will come from doing MPU
24
24
i
The
1 (f1)
f2
CSI
memory address
and Phase 2
NMOS output signal must be tied to the and clock-driver NMOS output MPU, and the
clock-driver
|2
j\
also used as a sync signal to
to its dl input pin.
Phase 2
the system that the
MPU can write into.
NMOS
signal,
RAM.
RAM
TTL
type
PIAs and the
pins (E) of the
each
(f2) is
from the clock, for
signal
f2
but rather a
Clock
(f2)
data bus enable input pins of the
the
CSI
10
J
Phase
CSI
ACIA
L _ r ^
Fig. 10.5 Valid
10.6
24
est
»
WAJT3
PIA#-2
PIAJM
VMA
so.)
f2.
This
ACIA
In our sample system,
This
f2
a non-TTL-compatible clock
this is
TTL
f2
should be tied to the enable
in addition to it
will
any part of
should not be the same as
one of the chip
be tied to the
CS0
it
may
chips, there
MC6871A
is
clock chip has these outputs available.
RAM SZ
RAM*I
RAM* 3
MPU
02 QBE 01
37
10
10
3
CSO
(
CLOCK MC687IA
NMOS 01
10
CS0
CS0
—
36f
25 (
25
E
,
PIAJT3
PIAJTZ
PIAJFI
25
E
13 . i
NMOS 02 TTL
on
Notice that the TTL J2 is not required in the ROMs, be gated into a positive chip select if desired. In most clock usually a separate f2 TTL output signal. The Motorola
(Fig. 10.6).
although
selects
inputs of each
12
ACIA
3 2
,
14
E
Fig. 10.6
Phase
1
and phase 2 clock
signals
E
System Configuration
10.7
Unused Inputs
of the
MPU
HALT
debugging purposes),
should be tied to the
normal execution
BA
HALT input is usually used for external control
Since the
(for
+5-V
213
this input pin for the general
system
input power through a 3.3-k resistor to permit
(Fig. 10.7).
Since this
an output
is
some
to be used as a signal to
line, it
should be
left
alone unless
it is
external device.
+5V MPU
?3JK 2
HALT
7_
BA
5 VOLT
+5V
1
6ND
_
71 iU
6ND
Fig. 10.7
10.8
Unused
inputs
Address Lines When
device
POWER
+
8
we must remember
the address lines are assigned,
to have
is
its
own unique
that each
address.
Recall that the four chip selects (CS) in the ROMs are mask-programmable, that is, defined by the customer and manufactured into the device. In our sample system (Fig. 10.8), we will assume the presence of three positive chip selects and one negative chip select in the ROMs. A positive chip select (CS) requires a -f 2-V signal to activate the input. A negative chip select (CS) requires a 0-V level to activate. Recall that a has ten address lines to
ROM
address 1,024 different locations in the
which
ROM
the other lines
is
addressed, our goal
is
ROM.
to select a
ROM while making sure that
ROMs in the system are not activated, and then, with MPU address
A0 through
A9, to
Since the chip selects determine
select
A9, which are connected to an address in that ROM.
In assigning address lines to the applied as for the
ROMs.
Since the
ROM address lines A0 through
RAMs,
RAMS
the same basic philosophy is have 128 separate locations,
MPU address lines A0 A6 will be tied to RAM address lines A0 through A6. The RAM chip
however, seven address lines are required. Therefore,
through to
(two positive and four negative) are then tied to the MPU address lines produce the desired address. Also recall that the TTL phase 2 (\2) signal
is
applied to a positive chip select (CS0).
selects
The PIAs have only two tied to
register selects available,
MPU address lines A0 and Al.
to be addressed with only
two
Remember
register selects,
and these must be
that there are six registers
an action accomplished with the
Basic Microprocessors and the 6800
214
aid of control register bit 2, as
shown
in
Chap.
9.
The remaining chip
selects
of the PI A (two positive and one negative) are tied to the proper MPU address line to achieve the desired address.
The ACIA has only one The remaining chip
selects
register select tied to
(two positive and
MPU address line A0.
one negative) are tied to the
MPU
address line to achieve the desired address. will be at addresses 0000 through In our sample system, the 8FFF; the PIAs, at addresses through 01 7F; the ROMs, at addresses 8400 4010 through 4013; and the and 4004 through 4007, 4008 through 400B,
proper
RAMs
ACIA,
at addresses
4020 and 4021. for wiring up a complete system using these addresses
The procedure is
as follows:
ACIA
RAM
02
—
\°
CSO C5i
J
™
A6
CS3
CS4 CS5
Fig. 10.8
Sample system
With the use of a system layout work sheet such as that shown in Fig. 10.9, list all devices and place an X in the columns that represent the MPU address lines to which the devices must be tied. The A0 through A6 Step 1
RAMs must be tied to MPU address lines A0 through A6. All A0 through A9 pins of the ROMs must be tied to MPU address lines A0 through
pins of
A9. of
all
RS0 pins
all
of all
PIAs must be
PIAs must be
must be
tied to
tied to
MPU 15
14
MPU address line A0. The RSI
MPU address line Al.
The RS
pin of the
address line A0.
MPU Device
tied to
13
12
RAM#1 RAM #2 RAM #3 ROM#1 ROM #2 ROM #3
11
Address Lines
10
9
X X X
8
Address
(A0-A15) 7
X X
X
X
X
X
From
6
5
4
3
2
1
X X X
X
X
X
X
X X
X X
X X X
X X
X
X X
X
X
X X X
X X X
X X X
X X X
X
X X X
X
X X
X X
RSI RS0
PIA#1 PIA#2 PIA#3
RS1 RS0 RSI RSQ
RS
ACIA#1
Fig. 10.9
System layout work sheet (Step
1)
To
pins
ACIA
215
System Configuration Step 2
Assign the three positive selects of
ROM #
1
to the appro-
priate
MPU address lines to achieve the proper address. The ROM #
range
is
from 8400 through 87FF. To get an 8000 address, a chip
1
address
select
must
ROM
MPU
address, 8400, address line A15 (Fig. 10.10). The lowest be tied to address line 10. The can be achieved by tying a positive chip select to remaining positive chip select will be tied to -I- 5 V since it is not needed for
A
MPU
that if A15 and A 10 are both high and all an address of 8400 is generated. If A15 and A10 through A9 are also high, an address of 87FF is generated.
addressing. Notice in
remaining address are high,
and
A0
ROM #1
lines low,
MPU Oevice
RAM#1 RAM #2 RAM #3 ROM#1 ROM #2 ROM #3
15
14
13
12
Address Lines
10
11
9
A»- A15)
8
7
5
4
3
2
1
X X
X X X
X X
X X X
X X X
X X X
X X X
X X X
X X
X X X
X X
X X
X
X
X
X CS
CS
X X
X X
X
X
X X X
Address
From
6
X X
X
X
To
X X X
PIA#1
RSI RS0
PIA#2 PIA#3
RSI RS0
6400 87FF
RSI R?Q
ACIA#1
RS
Fig. 10.10
Step 2
Assign the three positive and one negative chip selects of
Step 3
ROM #2 to the appropriate MPU address line to achieve the proper address from 8800 through 8BFF. for ROM #2. The ROM #2 address range Again, a positive chip select must be tied to MPU address line A 15. To achieve the beginning address of 8800, a positive chip select must be tied to MPU is
address line All.
The remaining
positive chip select pin
must be
tied to the
+ 5-V power supply. Now recall the earlier requirement that each device have its own unique address. If A 15, A 10, and All were all high, both ROM #1 and ROM #2 would be addressed. To prevent this from happening, a negative chip select of
ROM # ROM
1
chip select from
can be
#2, MPU
Device
RAM #1 RAM #2 RAM #3 ROM#1 ROM #2 ROM #3
15
14
13
12
11
to
MPU
Address Lines
10
CS
C5
CS
CS
CS
CS
MPU address line All, and a negative
tied to
9
X X X
8
X X X
address line
A10
(Fig. 10.11).
(A0- A15)
Address
6
5
4
3
2
1
X X X
X
X X
X X X
X
X
X X
X X X
X X X X
X
X X X
X X X X
X X
X
X X X X X
X
X
7
X
From
X X X X X X
PIA#1
RS1 RS0
PIA#2
RS1 RS0
A #3
RSI RSQ
PI
ACIA #1
RS
Fig. 10.11
Step 3
To
8400 87FF 8800 8BFF
Now
if
Basic Microprocessors and the 6800
216
MPU address line Al
1
ROM #
goes high,
pin needs a low signal to activate.
MPU
1
The same
cannot be activated since is
true regarding
A
address line 10. Also notice that with remaining address lines low, the address of 8800
A 10
are high,
is
low and
A0
through
A9
its
Al 1
ROM #2 with
A15 and All
high and
all
A15 and Al 1 address of 8BFF is
achieved. If
is
are high; thus
achieved.
Assign the three positive and one negative chip selects of
Step 4
ROM #3
to the appropriate
MPU
address lines to achieve addresses
through 8FFF. If a positive chip select
and
A 10,
the address of
8C00
is
is
tied to
8C00
MPU address lines A 15, Al
1,
achieved (Fig. 10.12). In this case, since the
ROM #3 is not used, must be tied to ground. If A 15, A 10 are high, and A0 through A9 all low, the address of 8C00 is achieved. If A 15, Al A 10, and A0 through A9 are high, the address of 8FFF negative chip select of
it
All, and
1,
is
ROM #3 addressed. (NOTE: Recall that MPU puts the address bus at FFFE on restart, a ROM location is
achieved. Also notice that only
when
the
By reviewing the above chart,
addressed. is
is
on the address
it
should be obvious that when
bus, the next to last location in
ROM #3
is
FFFE
addressed.
The
MPU will next put all address lines high to address the last location of ROM #3. The contents of these last two locations in the last ROM are placed in the program counter that tells the MPU where to get its first instruction.) MPU Device
RAM#1 RAM #2 RAM #3 ROM#1 ROM #2 ROM #3
IS
14
13
12
11
Address Lines
10
9
8
(Ad- A15) 7
5
4
3
2
1
X
X X X
X
X
X
X
X X
X X
X X
X X
X X
X X X
X X X
X
X X X
X X
X X cs
Cl
cs
cs
CS
cs
cs
CS
cs
X X X
X X X
Address
X X
X X
X
X
PIA#1 PIA#2 PIA#3
X X X
X
8400 87FF 8800 8BFF 8C00 8FFF
RS1 RS0
RSI RSQ
RS
Fig. 10.12
Step 5
X X
X
To
RSI RS0
ACIA#1
PIAs
From
6
Step 4
Assign the two positive and one negative chip selects of the 4004 through 4007, 4008 through 400B, and 4010
to achieve addresses
through 4013 by tying the CS1 chip selects of each PI A to MPU address line A 14 (Fig. 10.13). If CS0 of PIA # is tied to MPU address line A2; CS0 of PI A #2, to MPU address line A3; and CS0 of PIA #3, to MPU address line 1
A4, the above PIA addresses are achieved. By tying the negative chip select PIA to MPU address line A 15, the PIAs will not be addressed if a has been addressed. Again, if A 14 and A2 are high and all remaining
of each
ROM MPU address lines low, the address of 4Q04
is achieved. If MPU address lines A 14, A2, Al, and A0 are high and the remaining address lines low, the address
4007
#3,
is it
By going through the same analysis for PIA #2 and PIA be seen that the assigned addresses are achieved. (NOTE: Although
achieved.
will
System Configuration
CS1
is
shown
A 14 ANDed
tied to
with
MPU address line A 14,
VMA,
RAM#1 RAM #2 RAM #3 ROM#1 ROM #2 ROM #3 PIA#1 PIA#2 PIA#3
14
13
12
Address Lines
10
11
CS
cl
CS
CS
CS
CS
CS
CS
CS
CS2
CS1
CS2
CS1
CS2
CS1
9
7
X X
X X X
Fig. 10.14).
(A0- A15)
8
X X X
X
output of
this line is really the
—see
as discussed earlier
MPU 15
Device
217
Address
6
5
4
3
X X X
X X X
X X X
X
X
X
X
X
X
X X
X X
X
2
1
X
X
X
X X X X
X
X X X X
X
X
From
To
X X
X
X X
X
8400 87FF
X
8800 8BFF 8CO0 8FFF
X
cso RSI RS0 4004 4007 RSI RS0 4008 400B RSI RSO 4010 4013
cso cso
ACIA#1
RS
Step 5
Fig. 10.13
AI4TIED TO CSI OF ALL PIAs
VMA-
A14 ANDed
Fig. 10.14
Step 6
A5 and CSI
Assign chip select
CSO
with
of the
MPU address line A14 (Fig.
to
VMA
ACIA to MPU address line CS2 of the ACIA is tied
10.15).
MPU address line A15 to prevent the ACIA from being addressed when ROM addressed. This will achieve the ACIA addresses desired (4020 and
to
a
is
4021).
MPU Device
RAM#1 RAM #2 RAM #3 ROM#1 ROM #2 ROM #3
15
14
13
12
11
Address Lines
10
CS
CS
CS
CS
CS
CS
CS
CS
CS
PIA#1 PIA#2 PI A #3
CSl
CSI
CS2
CS1
CS2
CSI
ACIA#1
csl
CSI
9
X X X
8
X X
X
(A0- A15) 7
X X X
To
5
4
3
2
1
X X
X X X
X
X
X X X
X X
X X X
X X X
X X X
X X X
X X X
X X X
X X X
X X
X
8400 87FF
X
8800 8BFF
X
X
8C00 8FFF
X
X X
cso RSI RSO 4004 4007 CSO CSO
RSI RSO 4008 400B RS1 RSO 4010 4013
RS
CSO
Fig. 10.15
Step 7
Address
From
6
4020 4021
Step 6
Assign the four negative and two positive chip selects of
RAM to the proper MPU address lines to achieve the desired addresses. Since A15 high when a ROM addressed and A 14 high when PIAs and the ACIA are addressed, a negative chip select from each RAM should be tied to MPU address lines A 14 and A15 to prevent a RAM from being accidently each
is
addressed
ments
when a ROM, PIA,
is
or
is
ACIA
is
addressed. Notice the
in Fig. 10.16 are assigned so that only
one
CS
assign-
RAM can be addressed at
Basic Microprocessors and the 6800
218
any one time. The CSO of all RAMS is tied to the TTL f2 signal from t he clock. The CS3 on #1 is tied to the +5-V power supply. The CS2 of and #2 #3 will be tied to system ground.
RAM RAM
RAM
MPU Device
15
14
13
12
11
Address Lines
10
8
9
(A0- A15) X X
X
X X X
X
X
X X X
X X X
X X X
X X X
CS)
CS3 est
X X X
X X X
PIA#1 PIA#2 PIA#3
CS2
CSI
CS2
CS1
CS2
CSI
ACIA#1
csl
CSI
CS
CS
CS
CS
CS
CS
X X
X
X
CS3
X
X X X
X
OOFF
8800 8BFF 8C00 8FFF
CSO RSI RSO 4004 4007 CSO
CSO
RS1 RSO 4008 400B RS1 RSO 4010 4013
RS
CSO
Fig. 10.16
You have now
0I7F
8400 87FF
1
CS5 CS4
X
X X X
2
CS5
X
X X X
3
X X X
CS
OIOO
4
CS2 csi
CS
007F
X X
0000 0080
5
CS5 CS4
CS
To
X X X
6
RAM#1 RAM #2 RAM #3 ROM#1 ROM #2 ROM #3
CS4
Address
From
7
4020 4021
Step 7
wired up a complete system. If different addresses are
to be assigned, start with the
first
chart in Fig. 10.9 and follow the same
procedure.
Problems Using the chart below, configure a system having an MPU, sixteen input and operating sixteen output lines, 256 bytes of RAM, two ACIAs, and a must start at address 0000. The PIAs must system of 3,980 bytes. The start at address 1004, with the ACIAs immediately following the PIAs. The
ROM
RAM
last
address of the
chip selects for the
ROM must be 4FFF. The selection of positive or negative ROM will be determined by you. However, only one device
may be
addressed at any one time. Using the chart below, configure a system with an MPU, eight input and eight for scratchpad memory, and 2,048 output lines, one ACIA, 128 bytes of for the operating system. You determine the addresses, but only bytes of
RAM
ROM
one device may be addressed your choice.
at
any one time. The
ROM chip selects are also
System Layout Worksheel Address Lines (Af-A15) 7 6 5 4 3 8 15 14 13 12 11 10 9
Address
MPU
Device
2
1
i
From
To
11
Example Programs One of the best techniques for learning about microcomputer systems to study example programs. In this chapter, several example programs will be presented. Some that don't really do much nevertheless illuminate one is
aspect or another of such systems. All programs are geared to the
system and are presented for
11.1
M6800
purposes only.
illustrative
Add Four Numbers Program for adding four
The purpose of this program
numbers
is
(1) to
show
how instructions are structured in a program in machine language, (2) to show how the same program is written in M6800 source language, (3) to show the source program after it has been assembled by the M6800 assembler, and (4) to
compare the assembled output, which
is
in hex,
with the machine language
solution.
Problem: Write a program, in machine language and in
M6800 source
language, to add the decimal numbers 25, 35, 50, and 17. Store the answer at location OA. Assemble the source program, and compare the assembled
RAM
program with the machine language program.
Machine Language Solution SOLUTION:
MEMORY LOCATION
3510 = 1000112 5010 = 1100102
=
2316
=
3216
1710 = 0100012 2510 = 0110012
=
"16
=
1916
MACHINE
COMMENT
LANGUAGE
(HEX)
(BINARY)
(HEX)
000B OOOC 0000 000E 000F 0010
10000110 00011001 10001011 00100011
(86)
10001011 00110010 10001011 00010001 10010111 00001010
(8B)
0011
0012 0013 0014
LOA A IMM
(11)
DATA TO BE PUT IN A ADD A IMM DATA TO BE ADDED TO A ADD A IMM DATA TO BE ADDED TO A ADD A IMM DATA TO BE ADDEO TO A
(97)
STORES A
(0A)
0A
(19)
(8B) (23)
(32)
(8B)
219
IN
LOCATION
220
Basic Microprocessors and the 6800
Program Written
in
M6800 Source Language 100 110
120 130 140 150 160
170 180
NAM ADD4NR ORG
$A
TEMP RMB LDA A #25 ADD A #35 ADD A #$32 ADD A #% 10001 STA A TEMP END 1
Notice in the source language statements
added may be
listed in decimal, hex, octal,
how
or binary.
the
numbers
to be
The assembler
will
convert them to machine language for you. However, you must indicate to the
assembler what base system your number is in, that is $32 indicates hex 32. Both 25 and 35 are in decimal, and 10001 indicates that the number is already in binary. The symbol indicates the immediate mode of addressing.
%
#
Previous Source Program Assembled by
00100 00110 00120 00130 00140 00150 00160 00170 00180
M6800 Assembler
NAM 000A 000A 0001 000B 86 19 000D 8B 23 000F 8B 32 0011 8B 11 0013
i
97
ADD4NR $A 1
A #25 A #35 A #$32 A #% 10001 STA A TEMP END
0A
L
i
ORG TEMP RMB LDA ADD ADD ADD
3peranc1
SOURCE
Line
nu mber
Instruction
PROGRAM
Address
11.2
Program to Clear Nine Memory Locations This program illustrates
utive
memory
locations.
hex 70 through
two
78.
how the index register is used to clear consecclears the nine memory locations from
The program
A solution with its corresponding flowchart (Fig.
alternative solutions are presented.
11.1)
and
221
Example Programs Solution
100
NAM CLM
110
OPT
M
120
ORG LDX
$500
130
#$70
CLR
140 LI
0,X
150
INX
160
170
CPX #$79 BNE LI
180
END
START
'
'
INITIALIZE
START
MEMORY ADDRESS
'
'
CLEAR A MEMORY LOCATION
\ '
INCREMENT
MEMORY ADDRESS
/ \l
LA ST
v JEL_
LOW TION^
f
STOP
J
NO
Fig. 11.1 Flowchart of solution
Each time the program comes
to the
"CPX #$79"
contents of the index register will be compared with hex are not equal, the
"BNE LI"
instruction causes the
instruction, the
number
program
79. If they
to return to the
instruction that contains the label "LI".
When Notice that the
the index register
"CPX"
is
equal to hex 79, the program will stop.
Z bit of the condition code Z bit determine whether it
instruction resulted in the
register being set or reset.
The contents of the
branches back or goes forward.
222
Basic Microprocessors and the 6800
Alternative Solution 1
100
NAM CLM
110
OPT
120
ORG $500 LDX #$9
130
140 LI
150 160
170
Alternative Solution
CLR
DEX BNE END
6F,X
LI
2 100
NAM CLM
110
OPT
M
120
ORG
$500
130
LDS
#$78
140
CLR A
MORE PSH A
150
11.3
M
160
TSX
170 180
CPX #$70 BNE MORE
190
END
Program to Clear Locations 00 Through Hex FF This program
(in this case,
memory
illustrates
locations
how
large blocks of
memory can be
cleared
00 through hex FF).
Solution
100
NAM CLM
110
OPT
M
120
ORG LDX
$500
130 140
150 160
#0 CLR A AGAIN STA A
180
CPX BNE
190
END
170
0,X
INX #$100
AGAIN
Again, the "CPX" instruction sets or resets the bit of the condition code register that the "BNE" instruction will use to determine whether to branch back or continue. This solution uses 12 bytes and takes 4,357 cycles.
Example Programs
223
Alternative Solution 1
100
NAM CLM
110
OPT
M
120
ORG LDX
$500
130 140
#0 AGAIN CLR
150
INX
160 170
CPX BNE
180
END
0,X
#$100
AGAIN
This solution uses 11 bytes and takes 4,611 cycles.
Alternative Solution
2 100
NAM CLM
110
OPT
M
120
ORG LDX
$500
130 140 150 160 170
180
#$FF AGAIN CLR 0,X DEX BNE AGAIN CLR 0,X
END
This solution uses ten bytes and takes 3,835 cycles.
11.4
Load Memory with a Data Table (Ascending) This program illustrates
loaded into the
memory
how
the data table
locations given.
ADDR
DATA
0000
00
0001
01
0002 0003
02 03
00FD 00FE 00FF
FD FE FF
shown below can be
Basic Microprocessors and the 6800
224 Solution
100
NAM
STT
110
OPT
M
120
ORG $500 LDX #0 CLR A
130 140 150 160 170
INC INX
0,X
A
190
CPX #$100 BNE NEXT
200
END
180
11.5
NEXT STA A
Load Memory with a Data Table (Descending)
The following two programs below can be loaded into memory.
illustrate
ADDR
DATA
0000 0001
FF FE
0002
FD
00FD 00FE 00FF
02
how
01
00
Solution 1
100
NAM
STT
110
OPT
M
120
ORG LDA LDX
$500
130 140 150 160 170
A #$5FF #0 AGAIN STA A 0,X INX
180
DEC BNE
190
STA
200
END
A AGAIN A $FF
the data table
shown
Example Programs Solution
2 100
NAM
STT
110
OPT
M
120
ORG
$500
130 140 150
11.6
225
#$FF CLR A AGAIN PSH A LDS
160
INC
170
BNE
180
END
Move $80 Bytes
A AGAIN
of Data
This program moves hex 80 bytes of data from
through 7F (shown below) to
A00R
memory
memory
OATA
A0DR
0000
OATA
0100
A
MPU
007F
0I7F
BEFORE MOVE
AFTER MOVE
Solution
100
NAM MOV
110
OPT
120 130
140 150 160
M
ORG $500 LDX #0 MORE LDA A INX STA
A
0,X
$FF,X
180
CPX #$80 BNE MORE
190
END
170
locations
locations hex 100 through hex 17F.
Basic Microprocessors and the 6800
226
11.7
Program to Move a Constant Write a program for the following sequence: Begin with data 7F and load
1.
it
into the
memory location 50. 2. From location 50, load the data extended memory location 0113.
A accumulator; then store
the data in
it
in
into the
B accumulator;
then store
Reload data into the A accumulator from the extended memory it in location 6A, and then jump back to the beginning.
3.
location, store
Assume with
RAM
through
that this
program
will
be used in a microcomputer system addresses 800
addresses 000 through 200 (512 bytes) and
FFF
(2,048 bytes). All
numbers
in the source
ROM
program are
in hex.
Source Program 100
NAM
LTR1
101
OPT
MEM
ORG
$6A
102 103 105
110 120
TEMP RMB
ORG
$0800
START LDA A STA A $50
130
LDA B
140
STA
150
B
$7F
START OF PROGRAM
$50 $0113 $0113
LDA A A TEMP
190
STA JMP
200
END
180
1
START
Assembled Program
00100 00101 00102 00103 00105 00110 00120 00130 00140 00150 00180 00190 00200
006A 006A 0001 0800 0800 86 7F 0802 97 50 0804 D6 50 0806 F7 0113 0809 B6 0113
080C 97 6A 080E 7E 0800
NAM
LTR1
OPT
MEM
ORG $6A TEMP RMB ORG $0800 START LDA A #$7F START OF PROGRAM STA A $50 LDA B $50 ADDRESS OF DATA 1
STA B
$0113
LDA A $0113 STA A TEMP JMP
END
START
227
Example Programs
11.8 Program Numbers
to Subtract Absolute Values of
The purpose of this program the absolute value of If the result is less
Y
to calculate a quantity
than or equal to zero, set
Z = Z =
A
is
subtracted from the absolute value of
|W|
-
Z
if |W|
flowchart for this program
is
shown
YES
—
Ky 1
A-B
YES
B
0-B— B
'
—
A
XX
^ 1
NO
NO
—
'
A—
Fig. 11.2 Flowchart of
|Y|
in Fig. 11.2.
0-A—
Y
|Y|
program
Z
W
equal to zero.
if |W|
|Y|
Two
(
that will be |W|
—
|Y| ).
Basic Microprocessors and the 6800
228
Source Program for Absolute Value Problem 100
NAM
ABS
110
OPT
M
120
ORG O
130
WRMB
1
140
Y RMB
1
150
Z
RMB ORG $0500
160
1
170
LDA
AW
180
BPL
Zl IS
190
200 210 220 230 240
250 260 270 280
W POSITIVE?
NEG A W WAS NEG MAKE Zl LDA B Y
POS.
Z2 IS Y POSITIVE? NEG B Y WAS NEG, MAKE POS. Z2 SBA SUBTRACT Y FROM W BGT Z3 IS Z POSITIVE? CLR A RESULT WAS ZERO OR NEG. Z3 STA A Z STORE ANSWER IN Z. BRA *
BPL
MON
Assembled Program for Absolute Value Problem
00100 00110 00120 00130 00140 00150 00160 00170 00180 00190
0000 0000 0001 0001
0001 0001
0002 0500 0500 96 00 0502 2A 01 0504 40
NAM
ABS
OPT
M
ORG W RMB Y RMB Z RMB ORG LDA A BPL
1 1
1
$0500
W Zl
NEG A
IS W POSITIVE? W WAS NEG, MAKE
POS. 00200 00210 00220 00230 00240 00250
0505 0507 0509
D6 01 2A 01
050A
10
Zl
LDA B Y BPL
Z2
NEG B
50
Z2 SBA
050B 2E 01
050D 4F
BGT CLR A
Z3
Y POSITIVE? Y WAS NEG, MAKE POS. SUBTRACT Y FROM W IS
IS
Z POSITIVE?
RESULT WAS ZERO OR NEG.
00260 050E 97 02 Z3 00270 0510 20 FE 00280
STA A Z
BRA
MON
*
STORE ANSWER IN
Z.
Example Programs
229
11.9 Multiplication Subroutine This subroutine multiplies two eight-bit unsigned binary numbers (producing a 16-bit result). The product of the two eight-bit numbers is formed by shifting the multiplier one bit to the right and checking for a "1" or "0". If a
"1"
is
present, the multiplicand
multiplicand
is
added to the product (answer). The
is
then shifted one bit to the
This has the
left.
effect
of multiplying
The multiplier is again shifted one bit to the right and
the multiplicand by two.
the shifted bit checked for a "1" or "0". If it
a "1", the shifted multiplicand
is
added to the product. The process is repeated until the multiplier has no more "l"s remaining. When no more "l"s remain in the multiplier, the problem is finished and the product is the final product. For example, suppose that the decimal numbers 170 and 850 were to is
be multiplied. Then, 170 10
X
5,o
170,0
5
= 850 = AA, = 05,
10
6
6
1010
1010
Multiplicand (M)
0000
0101
Multiplier (N)
This
1
This
1
requires the multiplicand
M to be added to product.
requires the multiplicand shifted
left
twice (4
X M) to
be added to the product. Since
all
problem
remaining higher is
1010 1010 10 1010 10 11 3
of the multiplier are zero, the
16
5, 6
M 4
X
M
352, 6
=
850,0
0101 0010 2
5
AA X The flowchart
bits
finished.
=
for this multiplication subroutine
is
shown
in Fig.
Subroutine
NAM CMULT
100 1
10
220
OPT M,S
********************* REV
BAINTER
130
*
140
*
150
*
THIS SUBROUTINE MULTIPLIES
160
*
THE MULTIPLICAND
003 11-10-75
IS
TWO
8
BIT BYTES.
STORED IN BYTE
NB1.
1
1.3.
Basic Microprocessors and the 6800
230
CLEAR TEMP RAM LOCATIONS
SHIFT
MULTIPLIER RIGHT ONE BIT
SHIFT
MULTIPLICAND LEFT ONE BIT
ADO MULTIPLICAND TO ANSWER
Fig. 11.3 Flowchart of multiplication subroutine
170
*
180
*
190
*
200 2io 220 230 240 250 260 270
*
THE MULTIPLIER IS STORED IN BYTE NB2. THE RESULT IS STORED IN BYTES ANS2 AND ANS2 IS THE UPPER BYTE OF THE RESULT. ANSI IS THE LOWER BYTE OF THE RESULT.
ANSI.
********************* SPC
1
ORG NB1A RMB
1 SHIFT MULTIPLICAND STORE NB1 RMB 1 MULTIPLICAND NB2 RMB 1 MULTIPLIER ANS2 RMB 1 UPPER BYTE OF RESULT
231
Example Programs
ANSI SPC
280 290 300 310 330 340 350 360 370 380
RMB LOWER BYTE OF RESULT 1
1
ORG
$10
SPC
1
MULT CLR A CLEAR ANSWER & STA A NB1A STA A ANSI STA A ANS2 LDA A NB2 NB2 = MULTIPLIER BRA LOOP1 SPC
385
SHIFT AREAS
1
LOOP2 ASL NB1 SHIFT MULTIPLICAND LEFT
390 400 410 420 430 440 450 460 470 480 490 500 510 520
ROL NB1 A UPPER BYTE OF MULTIPLICAND LOOP1 LSR A SHIFT MULTIPLIER RIGHT FCC NOADD SHIFT AND DON'T ADD LDA B ANSI ADD SHIFTED MULTIPLICANDADD B NB1 to ANSI AND ANS2. STA B ANSI LOWER BYTE OF RESULT
LDA BANS2 ADC B NB1A ADD WITH CARRY STA TST
B ANS2 UPPER BYTE OF RESULT
A
NOADD BNE LOOP2 START SHIFTING AGAIN RTS
FINISHED!!!
MON
READY 11.10
System Program— BCD to LED As an example
of a system problem, assume a system composed of a
LED and a four-wire BCD signal. The object will be to use an M6800 to convert the BCD signal to the seven-segment code necessary to the
seven-segment
LED. Even though problem tant,
it
illustrates
the same task could be done with one TTL IC (7447), this not only a very simple complete system, but, more impor-
demonstrates one method of using a look-up table without getting The system configuration is shown in
entangled with more complex concepts. Fig. 11.4.
Source Listing
LIST
BCDLED 100
20:29EST
NAM BCDLED
11/10/75
232
Basic Microprocessors and the 6800
«- ^- t-
j
in
+
«-
O 5 £
Mi
—
O
1
D (WVb)
V0189W0W
BBBB33
I
I
§
£
O Q o CD 2 5 5 E £ 5 E I
I
co
0000
I
33IH
2 2
oc
O 2 «
nBS
ffll
UJ
o
00890W
r
111
111
SE
1° OC I-
VI
111
c 9 o 9 °
CO N «-
O
I
^88
60
tiiiiiisir O
©
I
o f n n
£J
oc
Example Programs
5gx -1
S5S8SS8&88 r j ~-
ilj rri
:r
«.n
8
.o r- CO Cr
-'.J
8s
a
0-i-00000-00
o
Q O u 1z UJ z a
U.O"-»-^000»-00
o
UjO»-0*-^«-©»-©r-
O
Oo>-oe>-ee-ooooooo »0.-Ot-0«-0 —
—
t-
»-
«-
w
»»»> »« >>>
TABLE FOLLOWS* FORM
BY TO 9033 0000 303F D311 3047 4D33
DATA BYTE FOLLOWED AN OUTPUT BYTE I MD I CAT I'VE OF THE OUTPUT BYTE BE GIVEM TO THE PIAPB 10000. $01 03, 10277.10331 .14201 . 1A42F
TABLE
FDB FDB ENDTAB FDB
JD311.13B29.1FF11.1FEC9 END OF TABLE 14D33
»«••««««« IRQ 3049 96 33 304B 2B 27
POLL
IS:
LDA A BMI
POLLING ROUTINE*
PIACB PEAK
GET CB VALLEY OR PEAK INTERRUPT?
INTERRUPT FOR VALLEY 'LIGHTS
304D 36 FO 304F 94 02 3051 D6 32 3053 C4 OF
3055 IB 3056 37 33 3053 305A 305C 305E 3060 3063 3064 3066 3063 306A
VALLEY LDA AND LDA AND ABA
96 30 91
03 27 06 37 03
PIAPB
PIAPA TEMP
STA
TEMP COUNT
STORE NEW DATA ZERO COUNTER GO BACK TO EXEC
»01
THIRD TINE MATCH?
CDUMT GOOD IN COUNT
IF SO, GO TO IF NOT, JUST
7C 0001
INC
SAME
INPUTS SANE AS LAST TINE? CLEARS INTERRUPT
SAME
RTI
27 04
Dl
01 01
INPUTS)
OUTPUT 4 BITS OF LIGHT DATA ONLY W-0 CHANGING MOTOR OUTPUTS
STA A
LDA B CMP B BE9
C6
«1 OF
LDA CMP BE* CLR
7F 0001 3B
«1F0 EXDUT PIAPB
3.
GOOD IN INC COUNTER
Example Programs 00900 00910 00930 00930 00940 00950 00960 00970 00990 00990 01000 01010 01020 01030 01040 01050 01060 01070 01090 01090 01100
RT1
306D 3B
'300DIN STft 306E 97 00 CLR 3070 7F 0001 PTI 9073 3B
ftND
I
PUT GOOD
EXINP COUNT
ft
RETURN BflTft
_
IN RftN
NTERRUPT FOP PERK OUTPUTS*****
•
3074 36 OF 3076 94 02 3073 D6 32 307ft C4 F0 807C IB 307D 97 32 307F 3B
PEAK
LDft
ft
AND
ft
LDft B ftND B
OUTPUT 4 BITS OF MOTOR DftTft WO CHftflGING LIGHT BflTft. ALSO CLEARS IMT
»90F EXOUT PIftPB
«*F0
ftBft
STft
ft
PIftPB
PTI •
»»»•»»»»•» »»>«»»»»>*OPT I ONftL NNI INTERRUPT******* CLR 3090 7F 0092 NHI HftfWUP NOP 3033 01 BRft 9034 20 F9
OHIO
PIftPB
TURN OFF
HftMGUP
GO TO SLEEP
••••••»»»»»»»S£T
01120 01130 01140 93F8 01 ISO 93F8 9049 01160 01170
11.12
241
ftLL
OUTPUTS
VECTORS IN UPPER RON******
•
0R6 FOB
993F9 POLL» 0000.NHI .RESTRT
HON
Time Delay Program (Short Delay)
It is often desirable to program time delay loops into your program, and there are several ways to do so. One technique is to load the A accumulator with a number and decrement it to zero. It takes two cycles to decrement the A accumulator and four cycles to determine if it has been decremented to zero, or a total of six cycles per decrement. A program to load the A accumulator and then decrement it to zero is shown below, and a flowchart is given in Fig.
11.10.
Program: Cycles
100
NAM TMR
110
OPT
120 130
140 150 160
M
ORG $8000 LDA A #$FF DAGN DEC A BNE DAGN END
2
4
FF is equal to 255 l0 the program will make 255 loops at each plus the two original cycles to load the A accumulator:
Since hex six cycles
2
,
255 loops® 6 cycles 1
loop
@
2 cycles
ea. ea.
= =
1,530 cycles
2 cycles 1,532
Basic Microprocessors and the 6800
242
C
START
J
V SET COUNTER
NUMBER (A ACCUM)
J
Idagn
\ DECREMENT COUNTER
NO
<
A-0
>
YES
Fig. 11.10 Flowchart of time delay
If each cycle takes
1
program
(short)
microsecond, then 1,532 cycles results in a delay of 1,532
microseconds.
11.13
Time Delay Program (Long Delay)
A
longer time delay
may be needed
to perform
some function such
as flashing a light every two seconds. Such functions can be accomplished with
the following program.
A
flowchart
is
given in Fig. 11.11.
Program Cycles
100
NAM
LTC
105
OPT
M
110
ORG
$3000
115
120
130 140 145
150 155
LOOP1 LDA A #4 LOOP2 LDX #$FFFF
2
AGN DEX BNE AGN
4 4
DEC A BNE LOOP2 END
3
2
4
Example Programs
C
START
243
J
SET LONG
COUNTER
NO. (X REGISTER)
AGN
DECREMENT A ACCUM
-»>END
program
Fig. 11.11 Flowchart of time delay
The
label
LOOP1
location to this routine
is
shown
when
as a
(long)
means of branching from some other
the time delay
is
needed.
To
calculate the time
up the number of cycles and For example, if one cycle = 1
required to go through this time delay, just add
multiply the result by the time for each cycle.
ms, then:
Instruction
LDA A #4 LDX #$FFFF DEX BNE AGN DEC A BNE LOOP2
No. of Times
No. of Cycles
Total
Executed
Each Time
Cycles
1
2
2 12
65535 X 4 65535 X 4
3 4 4
1048560 1048560
4 4
2 4
8 16
4
Total No. of Cycles
2097158
244
Basic Microprocessors and the 6800
C Fig. 11.12 Binary to
The product of 2,097,158
BCD
cycles
COMPLETE^
conversion flowchart
and
2,097,158 ms, or 2.09158 seconds. Therefore, to go through this loop.
(A
A
ms
per cycle
is
approximately
takes approximately 2 seconds
By changing the number loaded in the "short counter"
register) or the index register, the delay
11.14 Binary to
1 it
BCD
time can be varied.
Conversion Program*
standard technique for binary-to-BCD conversion
is
that of the
Add 3 algorithm. The technique requires a register containing the N-bit binary number and enough four-bit BCD registers to contain the maximum equivalent
BCD
number
checking each in is
for the initial binary number.
The conversion
BCD register for a value of 5 or greater.
starts
by
If this condition exists
one or all of these registers (initially this condition cannot exist), then a 3 added to those registers where the condition exists. Next, the registers are
shifted
left,
with the carry out of the previous register being the carry in to the BCD register is checked for values of 5 or greater.
next register. Again each
N
This sequence continues until the registers have been shifted times, where is the number of bits in the initial binary word. The BCD registers then
N
*Reprinted from Motorola AN-757, Analog-to-Digital Conversion Techniques with the
M6800 Microprocessor System,
by
Don
Aldridge.
Example Programs
245
BCD equivalent of the initial binary word. The example with an eight-bit binary word consisting of all *T's. This word is converted to the BCD equivalent of 255 by this technique. After eight shifts, the last binary bit has been shifted out of the binary register, and the hundreds,
contain the resulting
below
tens,
starts
and
units registers contain a 255.
The M6800 source program for performing this technique of binary to BCD conversion follows. The initial binary number is a 16-bit number and occupies memory locations MSB and LSB; this number is converted (see Figs. 11.12 and 11.13) to the equivalent BCD number in memory locations TENTSD, HNDTHD, and UNTTEN. Each of these memory locations contains
two BCD digits. Eighty-three memory locations are required for program
storage, with a
maximum
Hundreds
conversion taking 1.8 ms.
Tens
8-Bit Binary
Units
1 1
1
Shift Shift
Add 3
Shift
00 10 00 10 10 5
5
Total
2
1
1 1
1
to Units
Shift
00 11 00 11 111 10 10 10 1
1
1
1111 1111
Shift
Add 3
100
1
111 10 10 10 1
1
1000 000
1 1
1
1
1111111 111111 11111
to Units
Shift
1
Add 3
to
Tens
Shift
Add 3
to Units
Shift
_
Shifts
Fig. 11.13 Binary to
BCD
conversion
Source Program 10
NAM DWA21
20 OPTM 30 ORG 40 MSB RMB 1 50 LSB RMB 1 60 ORG $0010 70 UNTTEN RMB 1 80 HNDTHD RMB 1 90 TENTSD RMB 1 100 ORG $0F00 110 CLR UNTTEN
BINARY NUMBER MOST SIGNIFICANT 8 BITS
INITIAL
LEAST SIGNIFICANT 8 BITS
BOD RESULTS UNITS AND TENS DIGITS HUNDREDS AND THOUSANDS TENS OF THOUSANDS DIGIT "BEGINNING OF PROGRAM**
Basic Microprocessors and the 6800
246
120 CLR HNDTHD 130 CLR TENTSD 140 LDX #$0010 150 BEGIN LDA A UNTTEN 160 TAB 170 AND A #$0F 180 SUB A #$05 190 BMI AT 200 ADD B #$03 210 ATTBA 220 AND A #$0F0 230 SUB A #$50 240 BMI BT 250 ADD B #$30 260 BT STA B UNTTEN 270 LDA A HNDTHD 280 TAB 290 AND A #$0F 300 SUB A #$05 310 BMI CT 320 ADD B #$03 330 CT TBA 340 AND A #$0F0 350 SUB A #$50 360 BMI DT 370 ADD B #$30 380 DT STA B HNDTHD 390 LDA A TENTSD 400 TAB 410 SUB A #$05 420 BMI ET 430 ADD B #$03 440 ET STA B TENTSD 450 ASL LSB 460 ROL MSB 470 ROL UNTTEN 480 ROL HNDTHD 490 ROL TENTSD 500 DEX 510 BNE BEGIN 520 END 530 MON
11.15
TENS COMPARISON
HUNDREDS COMPARISON
TENS OF THOUSANDS COMPARISON
END OF CONVERSION CHECK
ACIA Memory Load/Dump Program Assume
It is
UNITS COMPARISON
that there are three 128
desired to load a 256-byte
address 0080. Then,
program
X
8
MCM6810 RAMs
into the
in a system.
two upper RAMs starting with
7 247
Example Programs
Hand
RAM
load:
Value
Loc.
0000 0001
—
Starting vector
Stopping vector (Last address
+
00
'
80
f /
0002 0003
,
/
0000 j
01
r 80 007F 0080
/
1)
00FF 0100
01 7F
After the hand-loading of the starting and stopping vectors, the load at program address 0900. When the program is executed by starting the
MPU
program has finished loading, the
CA2
line of
PIA1 will go low. This signal lamp to indicate the end
can be used to stop the tape recorder or turn off a of the loading process.
The memory dump program works
as follows:
The
start-and-stop
memory dump addresses or vectors are hand-loaded into RAM locations 0000, 0001, 0002, and 0003 in the same manner as in the previous load program. and Program execution begins at memory address 094B. The characters
AA
or placed on the tape in order to indicate the beginning of memory dump or listing. Each program character or byte is dumped via the ACIA and modem until the last memory location has been addressed and
55 are
first
dumped
dumped. When the dump operation is complete, the CA2 lead of PIA1 will go low, indicating dump complete. (See Figs. 11.14 and 11.15 for load and
dump
flowcharts.)
Source Program 1.000
2.000 3.000
4.000 5.000 6.000 7.000 8.000
NAM LDBOOT OPT M THIS PROGRAM LOADS OR DUMPS MEMORY PLACE START ADDRESS IN LOC 00 & 01 PLACE END ADDRESS + 1 IN LOC 02 & 03 IF ERROR OCCURS, CHECK LOC 04 & 05 FOR ADDRESS. ^CA2 STOPS DRIVE AT EOT OR ERROR. CB2 GIVES ERROR INDICATION. DUMP PROGRAM STARTS AT LOC 094B.
9.000 10.000 PIA1AC EQU $0805 11.000 PIA1BC EQU $0807 12.000 ACIAC EQU $0806
248 13.000 14.000 15.000 16.000 17.000 18.000 19.000
20.000 21.000
22.000 23.000 24.000 25.000 26.000 27.000
28.000 29.000
30.000 31.000 32.000 33.000 34.000 35.000 36.000 37.000
38.000 39.000 40.000 41.000 42.000 43.000 44.000 45.000 46.000 47.000 48.000 49.000 50.000 51.000
Basic Microprocessors and the 6800
ACIAD EQU $0809
ORG $0900 LDAA#$Q3 A ACIAC ACIA MASTER RESET LOAD START ADDRESS A #$19 ACIA 8 BITS EVEN PARITY A ACIAC LOOP LDA A ACIAC ROR A BCC LOOP RECEIVER FULL? LDA A ACIAD CMPAA CMP A #$AA IS FIRST CHAR "AA"? BNE LOOP BRANCH IF NOT LOOP 1 LDA A ACIAC ROR A BCC LOOP1 LDA A ACIAD CMP A #$55 IS SECOND CHAR "55"? BNE CMPAA IF NOT, TRY FOR AN "AA" LOOP2 LDA A ACIAC TAB TRANSFER A TO B AND B #$70 BNE ERROR BRANCH IF ERROR ROR A BCC LOOP2 LDA A ACIAD LOAD A CHAR FROM TAPE STA A 0,X STORE IN MEMORY INX INCREMENT ADDRESS CPX $02 LOAD COMPLETED? BNE LOOP2 GO GET MORE END LDA A #$30 STA A PIA1AC TURN OFF CA2 STA LDX LDA STA
$00
BRA* ERROR LDA A #$36 STA A PIA1BC TURN ON ERROR LIGHT STX $04 STORE ADR OF ERROR BRA END PAGE
*START OF DUMP PROGRAM A #$19 A ACIAC A #$AA *OUTPUT CONTROL CHAR 55.000 A ACIAD 56.000 LOOP5 LDA A ACIAC 57.000 ROR A 58.000 ROR A 59.000 BCC LOOP5 *XMIT BUFFER EMPTY? 60.000 LDA A #$55 OUTPUT SECOND CONTROL CHAR 61.000 STA A ACIAD 62.000 LOOP6 LDA A ACIAC 63.000 ROR A 64.000 ROR A 65.000 BCC LOOP6 *XMIT BUFFER EMPTY? 52.000 53.000 54.000
LDX LDA STA LDA STA
$00
Example Programs 66.000 67.000
LOOP4 LDA A
68.000
LOOP3 LDA A ACIAC
0,
X
OUTPUT CHAR TO TAPE
STAAACIAD
69.000 70.000
RORA RORA
71.000 72.000
BCC LOOP3
73.000 74.000 75.000 76.000
CPX $02 BNE LOOP4 BRA END
XMIT BUFFER EMPTY?
INX
MON
ADDRESS 0900
GED Fig. 11.14
Load flowchart
249
Basic Microprocessors and the 6800
250
f
START
ADDRESS 094B
J
SET CA2 OF PIA #\ LOW
( Fig. 11.15
Dump
EN
°
)
flowchart
Assembled Program 00010 00020 00030 00040 00050 00060 00070 00080 00090 00100 00110 00120 00130 00140 00150 00160 00170 00180 00190 00200 00210 00220 00230
NAM
LDBOOT
M PROGRAM LOADS OR DUMPS MEMORY OPT
THIS
PLACE START ADDRESS IN LOC 00 & 01 PLACE END ADDRESS + 1 IN LOC 02 & 03 IF ERROR OCCURS, CHECK LOC 04 & 05 FOR ADDRESS. CA2 STOPS DRIVE AT EOT OR ERROR. CB2 GIVES ERROR INDICATION. DUMP PROGRAM STARTS AT LOC 094B. 0805 0807 0806 0809 0900 0900 0902 0905 0907 0909
090C 090F 0910 0912
PIA1AC EQU PIA1BC EQU ACIAC EQU ACIAD EQU
$0805 $0807 $0806 $0809 $0900
ORG 86 03 B7 0806 DE 00 86 19 B7 0806 B6 0806 46 24 FA B6 0809
LOOP
LDA STA LDX LDA STA LDA
A A
A A A ROR A BCC LDA A
#$03 ACIAC
ACIA MASTER RESET
$00
LOAD START ADDRESS
#$19 ACIAC ACIAC
ACIA 8 BITS EVEN PARITY
LOOP
RECEIVER FULL?
ACIAD
Example Programs
AA
00240 0915 00250 0917 00260 0919 00270 091 C 00280 091 D 00290 091 F 00300 0922 00310 0924 00320 0926 00330 0929 00340 092A 00350 092C 00360 092E 00370 092F 00380 0931 00390 0934 00400 0936 00410 0937 00420 0939 00430 093B 00440 093D 00450 0940 00460 0942 00470 0944 00480 0947 00490 0949 00510 094B 00520 094D 00530 094F 00540 0952 00550 0954 00560 0957 00570 095A 00580 095B 00590 095C 00600 095E
81
00610 00620 00630 00640 00650 00660 00670 00680 00690 00700 00710 00720 00730 00740 00750 00760
B7 0809 B6 0806
26 F3 B6 0806 46 24 FA B6 0809 81 55 26 EF B6 0806
CMPAA CMP A BNE LOOP1
LOOP2
LDAA ROR A
#$AA LOOP
IS
FIRST
BRANCH
CHAR "AA"? IF NOT
ACIAC
BCC
LOOPT
LDAA CMP A
ACIAD
#$55
IS
SECOND CHAR
BNE
CMPAA
IF
NOT, TRY FOR AN "AA"
LDAA
ACIAC
"55"?
TRANSFER A TO B
16
TAB
C4 70
ANDB
#$70
BNE
ERROR
26 14 46 24 F5 B6 0809 A7 00 08 9C 02 26 EB 86 30 B7 0805 20 FE 86 36 B7 0807 DF 04 20 FO DE 00 86 19 B7 0806 86 AA B7 0809 B6 0806 46 46 24 F9 86 55
251
BRANCH
IF
ERROR
ROR A BCC
LOOP2
LDAA
ACIAD 0, X
STA A INX
CPX BNE
END
LDAA STA A BRA
ERROR LDAA STA A STX BRA LDX
LDAA STA A
LOOP5
$02
LOOP2 #$30 PIA1AC
$04
START OF DUMP PROGRAM
#$19 ACIAC
#$AA ACIAD ACIAC
BCC
TURN ON ERROR LIGHT STORE ADR OF ERROR
END $00
LDAA
LDAA
TURN OFF CA2
#$36 PIA1BC
STA A
LDAA ROR A ROR A
LOAD A CHAR FROM TAPE STORE IN MEMORY INCREMENT ADDRESS LOAD COMPLETED? GO GET MORE
LOOP5 #$55
OUTPUT CONTROL CHAR
XMIT BUFFER EMPTY? OUTPUT SECOND CONTROL CHAR
0960 0963 0966 0967 0968
096A 096C 096F 0972 0973 0974 0976 0977 0979
097B
46 46 24 F9 A6 00 B7 0809 B6 0806 46 46 24 F9 08 9C 02 26 EF 20 BE
STA A
LOOP6
LOOP4
LDAA ROR A ROR A BCC
LOOP6
XMIT BUFFER EMPTY?
LDAA
0,
X ACIAD ACIAC
OUTPUT CHAR TO TAPE
LOOP3
XMIT BUFFER EMPTY?
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