DRV11-J parallel line interface user's guide
EK-DRV1J-UG-002
digital equipment corporation • marlboro, massachusetts
1st Edition, December, 1979 2nd Edition, November; 1980
Copyright·c 1979, 1980 by Digital Equipment Corporation All Rights Reserved
The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual.
Printed in U.S.A.
This document was set on DIGITAL's DECset-8000 computerized typesetting system.
The foHowing are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DIGITAL DEC PDP DECUS UNIBUS DECLAB
DECsystem-lO DECSYSTEM-20 DIBOL EduSystem VAX VMS
MASSBUS OMNIBUS OSj8 RSTS RSX lAS ~1INC-ll
'1"80·1'5
CONTENTS Page CHAPTER 1
INTRODUCfION
1.1
1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.3.1 1.5.3.2 1.5.3.3 1.5.3.4 1.6
GENERAL DESCRIPTION ................................................................................ FEATURES ..................................... ~..................................................................... DOCUMENTATION............................................................................................ DIAGNOSTIC SOFTWARE ............................................................................... SPECIFICATIONS............................................................................................... Physical Specifications ............................. ............ ....... .......... ....... .................. Electrical Specifications...................................................... ...... .................. ... Environmental Specifications .............................................. ...... ... ..... ............ Operating and Storage Temperature Ranges ........................................ Relative Humidity............................................................... ... ..... ........... Airflow during Operation....................................................................... Altitude ................... 00............................................................................. INSTALLATION..................................................................................................
CHAPTER 2
FUNCfIONAL DESCRIPTION
2.1 2.2
GENERAL DESCRIPTION ................................................................................ CONTROL/STATUS REGISTERS ................................................................... DATA BUFFER REGISTERS............................................................................. INTERRUPT CONTROL .................................................................................... Functional Description ... ......... ....................................................................... Interrupt Controller Interface........................................................................ Interrupt Controller Operating Description................................................... Interrupt Control Reset ...... .................. .................. ...... ............... .... .... ........... Interrupt Control Register Description............................. ....... ...................... Status Register..... ............ .............. ........................................................ Command Register ............................................................................. ,... Mode Register........................................................................................ Interrupt Request Register (lRR) ............. ............................. ............... Interrupt Service Register (ISR) ........................................................... Interrupt Mask Register (IMR) ............................................................ Auto-Clear Register (ACR) .................. ........... ..... .... ........ ..................... Vector Address Memory........................................................................ OPERATING OPTIONS ...................................................................................... Interrupt Priority Mode Selection......................... ......... .......... ..... .......... ....... Individual Vector or Common Vector Mode .................................................. Interrupt or Polled (Flag) Mode........................... ..... ..................................... Mode Register Bit 3 ..... ................ ............ ...................................................... IRQ Polarity Option ....................................................................................... Register Preselection Option.......................................................................... Master Mask Option ...................................................................................... SYSTEM OPERATING SEQUENCE ............................ .......... .......................... COMMAND DESCRIPTIONS ........................................................................... Reset ................................................................................................................ Clear IRR and IMR ....................................................................................... Clear Single IMR and IRR Bit ...................................................................... Clear IMR ........... ...... ...... .......... ........ ........... ..................................................
1.2 1.3
2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 2.4.5.2 2.4.5.3 2.4.5.4 2.4.5.5 2.4.5.6 2.4.5.7 2.4.5.8 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4
lit
1-1 1-1 1~2
1-2 1-2 1-2 1-2 1-3 1-3 1-3 1-3 1-3 1-3
2-1 2-1 2-1 2-1 2-7 2-7 2-9 2-12 2-13 2-13 2-14 2-14 2-14 2-15 2-16 2-16 2-16 2-17 2-17 2-19 2-19 2-19 2-19 2-19 2-20 2-20 2-21 2-21 2-21 2-21 2-21
CONTENTS (Coot) Page 2.7.5 2.7.6 2.7.7 2.7.8 2.7.9 2.7.10 2.7.11 2.7.12 2.7.13 2.7.14 2.7.15 2.7.16 2.7.17 2.7.18 2.7.19 2.7.20
Clear Single IMR Bit ..................................................................................... Set IMR........ ....... ............. ..... ............................. ............ ................................ Set Single IMR Bit ................................................................................... ,. .... Clear IRR ....................................................................................................... Clear Single IRR Bit... ......... ............. ....... ....................... ................. .............. Set IRR ......... ....... ..... .......... ... ........................................................................ Set Single IRR Bit ......................................................................................... Clear Highest Priority ISR Bit .......................... ............................................ Clear ISR ....................................................................... ................... .......... ... Clear Single ISR Bit ...................................................................................... Load Mode Bits MO through M4 ................................................................... Control Mode Bits M5, M6 and M7 ...... .................................................. ...... Preselect IMR for Writing ............................................................................. Preselect ACR for Writing............................................................................. Preselect Vector Address Memory for Writing ............................................. Coding B2, B 1, BO Field Commands ......... .... .......................................... ......
CHAPTER 3
CONFIGURATION
.3.1 3.2 3.3 3.4 3.5
GENERAL DESCRIPTION ................................................................................ FACTORY CONFIGURATION ......................................................................... DEVICE ADDRESSES ........................................................................................ DEVICE ADDRESS JUMPERS.......................................................................... INTERRUPT VECTOR ADDRESSES...............................................................
CHAPTER 4
INTERFACING
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
INTERFACE CONNECTORS............................................................................ INPUT jOUTPUT SIGNAL FUNCTIONS ........................................................ INPUT jOUTPUT SIGNAL ASSERTION LEVELS ........................................ INPUT jOUTPUT SIGNAL LOOPBACK CONNECTIONS ........................... INTERFACE CABLE.. ............................................................... .... ........... ...... ..... INPUT/OUTPUT FUNCTION TIMING .......................................................... INPUT DATA OPERATION............................................................................... OUTPUT DATA OPERATION ........................................................................... INTERRUPT OPERATION ................................................................................
CHAPTERS
PROGRAMMING EXAMPLES
5.1 5.2 5.3 5.4
GENERAL DESCRIPTION ................................................................................ PROGRAMMED DATA TRANSFER WITHOUT HANDSHAKING ........... PROGRAMMED DATA TRANSFER WITH HANDSHAKING.................... INTERRUPT-DRIVEN TRANSFER .................................................................
CHAPTER 6
OPTIC ISOLATOR INTERFACE EXAMPLE
IV
2-22 2-22 2-22 2·22 2-22 2-22 2-23 2-23 2-23 2-23 2-23 2-23 2-24 2-24 2-24 2-25
3-1 3-1 3-1 3-5 3-5
4-1 4-1 4-1 4-5 4-5 4-5 4-9 4-9 4-9
5-1 5-1 5-1 5-3
FIGURES Figure No. 2-1 2-2
2-3 2-4 ....
~
L.-J
2-6 2-7
2-8 2-9 2-10 2-11 2-12
2-13 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 5-3 5-4 6-1
Tide DRV!l-J Block Diagram........................................................................................ CSRA Bit Assignments '" ....... ............. ...................................................... ......... ..... CSRB Bit Assignments............ .................................. ................. ....... ......... ........ .... CSRC Bit Assignments ............................................................... ........ .... ........... .... CSRD Bit Assignments. ................. ....... ......................................................... ........ Data Buffer Register Bit Assignments................................. .................................. Group 1 and Group 2 Interrupt Controller Interconnections.................. .......... ................................................................. Intergroup Priority Resolution Timing ................................................................... Interrupt Controller Block Diagram............................................ ....... .................... CSRA and CSRC Status Registers' Bit Assignments ........................................... Mode Register Bit Assignments ..................... .......... ......... ....................... .......... .... DRVl1~J Vector Address Format .......................................................................... Rotating Priority Mode.... ............................. ......................................................... DRYlI-J Jumper Locations ................................................................................... DRVII-J Device Address Format.......................................................................... DRYll-J I/O Connector Pin Locations................................................................. I/O Bus Interface, Simplified Schematic .............................................................. DRVll-J I/O Function Timing ............................................................................. Input Data Transfer Sequence ......................... ..... ....................... ... ... ............ ........ Output Data Transfer Sequence ............................................................................ Interrupt Sequence................................................................................................. Example of a Programmed Data Transfer without Handshaking ..................................................................................... Example of a Programmed Data Transfer with Handshaking... ....... ........................ ...... ..... ... ...... .... ................ ........ ... ...... Example of an Interrupt-Driven Output Program ..................... ............................ Example of an Interrupt-Driven Input Program ...................... .............................. Example of an Optic Isolator Interface..................................................................
Page 2-2 2-3 2-4 2-5 2=6 2-7 2-8 2-10 2-11 2-14 2-15 2-17 2-18 3-2 3-5 4-2
4-4 4-7 4-10 4-1 i 4-12 5-2 5-3 5-4 5-5 6-2
TABLFS Table No. 1-1 2-1 2-2
2-3 2-4 2-5 2-6 2-7 2-8 2-9
Title DRVII-J Module Pin Assignment ......................................................................... CSRA Bit Functions and Descriptions..... .... ................... ....................................... CSRB Bit Functions and Descriptions .. ....................................................... .......... CSRC Bit Functions and Descriptions................................................................... CSRD Bit Functions and Descriptions................................................................... Summary of Data Bus Transfers ............................................................................ Interrupt Control Register and Memory Summary ............................................... Fixed Priority Mode ...... ..... ...... ...................... ............. ........................................... Vector Address Memory Field Coding ................................................................... Command Register B2, BI. 80 Field Coding ......................................................... v
Page 1-4 2-3 2-4 2-5 2=6 2-12 2-13 2-17 2-25 2-25
TABLES (Coot) Table No. 2-10
3-1 3-2 3-3 4-1 4-2 4-3 4-4
Title
Page
DRV11-J Command Code Summary ..................................................................... 2-26 DRVII-J Factory Jumper Configuration................................................................ 3-3 DRV11-J Jumper Functions................................................................................... 3-4 DRVII-J Registers................................................................................................. 3-4 I/O Connector Pin Assignments ............................................................................ 4-2 I/O Signal Functions.............................................................................................. 4-5 DRVII-J Loopback Signal Connections................................................................ 4-6 I/O Function Timing Tolerance............................................................................. 4-8
VI
CHAPTER 1 INTRODUCTION 1.1 GE~ERAL DESCRIPTIO~ The DR V II-J is a double-height parallel line interface module designed for use in LSI-II microcomputer systems. It contains four programmable ports designated A. B. C and D. Each port contains 16 I/O lines and is capable of transferring a 16-bit word between the LSI-II bus and the user device(s}. Data word transfers in or out of the DR V II-J are accomplished by the assertion of two control signals at each port of the 0 R V II-J and two control signals asserted by the user device to its respective port. These control signals must be asserted in a protocol sequence while observing timing constraints to ensure an orderly data transfer. The protocol sequence is described in Chapter 2. The DR V II-J will also accept ir.terrupt requests from up to 16 1/0 lines to generate up to 16 individual vector addresses. This interrupt capability for real-time response makes it useful for sensor I/O applications. The DR V II-J may also be used as a general-purpose interface to custom devices. or two DR V II-Js may be connected together as a link between two LSI-II buses. The DRVII-J contains two programmable mode registers that provide a number of operating modes to customize the moduie configuration for different system applications. The module may be programmed for use in vectored-interrupt-driven systems or software-polled systems. When used in vectored interrupt systems. the module may be programmed to operate in either a fixed priority or a rotating priority resolution mode. In addition. the module may be programmed to generate either a common vector address or individual vector addresses in response to user device(s} interrupt requests. Additional operating options available under program control include the selection of an active high or active low interrupt request polarity. preselection of internal registers, and the selection of a master mask bit to arm or disarm the interrupt capability of the DR V I1-J. All of the operating modes and options are described in detail in Chapter 2. The DR V I1-J also contains two RA Ms that are used to store programmed interrupt vector addresses. One 8-bit RA M location is used to store each interrupt vector address. One vector address may be programmed for each of the 16 interrupt request inputs.
1.2 FEATLRES The DR V 11-J contains the following features. • • • • • •
Four 3-state 16-bit parallel I/O ports User-assigned device addresses Acceptance of up to 16 external interrupt requests Programmable interrupt vector addresses Program-controlled input/ output operations Programmable operating modes: Interrupt Controller Mode - Interrupt-driven Priority Modes - Fixed or Rotating Vector Address Selection - Individual or common vector
I-I
1.3 DOCUMENTATION I n addition to this user's guide, refer to the Field Maintenance Print Set, M POO866, for information on the DRVII-J module. 1.4 DIAGNOSTIC SOFTWARE Diagnostic software is available for troubleshooting, fault isolation, and verification at both the module level and system level. Two diagnostics are required for testing at the module level and these must be run in sequence. A DECX II module diagnostic is required to test the module at the system level. Turnaround cable BC05W-02 must be installed with a half twist to J I and J2 when running the module- and system-level diagnostics. The diagnostic software is designated as follows.
• • •
CVDRCAO Part I CVDRDAO Part 2 DECX 11 Module CXDRJAO
1.5 SPECIFICATIONS The following defines the physical, electrical and environmental specifications for the DRV II-J module. 1.5.1
1.5.2
Physical Specifications
Identification
M8049
Size
Double-height 22.8 cm X 13.2 cm (8.9 in X 5.2 in)
Electrical Specifications
Power
+5 Vdc ± 5% @ 1.8 A (maximum), 1.6 A (typical)
Bus loads
ac 2 dc I
I/O Signal Electrical Parameters:
Data Buffer 3-State Outputs
Data Buffer Inputs
V(OL) = 0.5 V @ I(OL) = 8 rnA V(Ol) = 0.4 V @ I(OL) = 4 rnA V(OH) = 2.4 V @ I(OH) = ...:2.6 rnA
I(lL) = -0.2 rnA @ V(IL) = 0.4 V V(IH) = 20 ~A @ V(lH) = 2.7 V
Protocol Signal Inputs
Protocol Signal 3-State Outputs V(OL) = 0.55 V @ I(Ol) = 64 rnA V(OH) = 2.4 V @ I(OH) = -15 rnA
1-2
Termination = 120 n I(IL) = -27 rnA @ V(IL) = 0.5 V I(lH) = 80 ~A @ V(IH) = 2.7 V
1.5.3 Enfironmental Specifications The DRVII-J module may be operated or stored in the following environmental conditions. 1.5.3.1
Operating and Storage Temperature Ranges
Operating range:
50 to 60 0 C (41 0 to 140 0 F)
Storage range:
-40 0 to 66 0 C (-40 0 to 150 0 F)
If the module is not within its operating temperature range, move it to an area within the range and allow it to stabilize for a minimum of five minutes before operating. Also, derate the maximum operating temperature by 10 C (1.8 0 F) for each 305 m (1000 ft) of altitude above 2440 m (8000 ft). 1.5.3.2
Relatbe Humidity
Storage:
10% to 90%, noncondensing
Operating:
10% to 90%, noncondensing
1.5.3.3 Airflow during Operation - Provide adequate airflow to limit the inlet-to-outlet temperature rise across the module to 50 C (9 0 F) when the inlet temperature is 60° C (140° F). For operation below 55 0 C (131 ° F), limit that rise to 10° C (18° F) maximum. 1.5.3.4
Altitude
Storage:
The module will not be mechanically or electrically damaged at altitudes up to 15,240 m (50,000 ft), 90 mm mercury.
Operating:
Up to 15,240 m (50,000 ft), 90 mm mercury. Note: Derate the maximum operating temperature by 10 C (1.8 0 F) for each 305 m (1000 ft) of altitude above 2440 m (8000 ft).
1.6 INSTALLA TION The DR V I1-J is a bus request level 4 module and must be installed in an LSI-! I backplane dual-option slot foHowing the rules for position-dependent interrupt priority configurations. In position-dependent configurations, peripheral devices with the highest priority must be installed closest to the processor and the remaining devices placed in the backplane in decreasing order of priority, with the lowest priority module farthest from the processor.
Before installing the module(s) in the backplane, check that the proper device address jumpers are installed. Three standard LSI-II bus addresses are reserved for the DRVII-Js. If the application requires more than three DR V 11-1s, the additional modules must be assigned addresses located in the user-reserved address space. Chapter 3 describes the address configuration procedure. The standard factory jumper configuration is described in Table 3-1, and Figure 3-2 shows the device address format. CAUTION DC power must not be applied to the backplane when installing or remofing modules. The DRVl!~'s functionality must be proved after installation by performing an acceptance test. The acceptance test consists first of running the basic system diagnostics and then running the DR V Il-J module-level diagnostics listed in Paragraph 1.4.
1-3
Module Pin Assignments The DRV11-J module pin assignments are described in Table I-I.
Table I-I
DRVII-J Module Pin Assignment Connector B
Connector A Side J Signal
Pin
Side I Signal
+5V NC GND NC BDOUTL BRPLY L
NC NC NC NC NC NC
A B C D F
+5V NC GND NC BDAL2L BDAL3L
NC NC NC NC NC NC
H J K L M N
BDAL4L BDAL5L BDAL6L BDAL7L BDAL8L BDAL9L
BIRQ 7 L NC NC GND NC NC
P R S
BDAL 10 L BDAL II L BDALI2L BDAL 13 L BDAL 14 L BDALI5L
BIRQ 5 L BIRQ 6 L NC NC NC NC
A B C D
NC NC NC NC NC NC
H J K
L M N
BDIN L BSYNC L BWTBT L BIRQ4 BIAKI L BIAKO L
NC NC NC GND NC NC
P R S T U V
BBS 7 L BDMGI L BDMGOL BINITL BDALO L BDALI L
E F
Side 2 Signal
Side 1 Signal
NOTE: 1. Connector A, pin A, side 1 corresponds to bus pin AA I. 2. NC = no connection.
1-4
Pin
E
T
U V
CHAPTER 2 FUNCTIONAL DESCRIPTION 2.1 GE:\IERAL DESCRIPTION The DRVII-J contains the logic necessary to provide communication between the LSI-II bus and up to four user devices in 16-bit word lengths via four I/O ports. Four control lines associated with each of the four ports ensure orderly information transfers. Word transfers are executed by programmed I/O operations or interrupt-driven routines. Write data is output by the DRVII-J to the I/O bus through 3-state data latches, and read data is input through unlatched bus buffers. Figure 2-1 shows the main logic functions performed by the 0 R V I1-J module.
All control/status and I/O data transfers take place over a bidirectional internal bus (TSD < 15:00» on the DRVII-J. The module contains four I/O buses, one for each port (A, B. C and D). Each port has an associated control/status register (CSRA, CSRB. CSRC or CSRD) that contains status information when read and command words when written. All ports have 16 bidirectional 3-state lines and perform controlled input/output operations. Note that port A is the only port that will perform bit interrupt functions in addition to input/ output data transfers. The 16 external interrupt requests are functionally divided into two groups of eight lines, referred to as group 1 and group 2. 2.2 CONTROL/STATUS REGISTERS The control/status registers (CSRA, CSRB, CSRC and CSRD) are read/write byte-addressable registers with bit assignments as shown in Figures 2-2, 2-3, 2-4 and 2-5. The function and description of the control/status register bits are described in Tables 2-1, 2-2, 2-3 and 2-4.
2.3 DATA BUFFER REGISTERS The four data buffer registers (DBRA, DBRB, DBRC and DBRD) are 16-bit word-addressable registers. They are used as latched output data buffers when the DRV Il-J is in output mode (write) and as unlatched bus buffers in input mode (read). The contents of the output data buffers may be examined while the DR V 11-J is in an output mode by performing a read operation of the input data buffers. This ability to examine the output data buffers in the output mode provides software access to the internal conditions of the 0 R V 11-J.
The latched output data buffer registers DRBA through DBRD are not cleared by BINIT. The bit assignment is the same for all registers and is shown in Figure 2-6. 2.4 INTERRUPT CONTROL The DRY11-J is capable of monitoring 16 lines to generate 16 vectored interrupts. The interrupt control is performed by a DeOO3 interrupt logic chip and interrupt controller chips. A functional description of the signals required to initiate interrupts and the DRY 11-J registers used for programming, reading and writing the internal registers of the interrupt controllers is given in Paragraph 2.4.1. An operating description of the interrupt controllers is given in Paragraph 2.4.2, and the internal registers of the interrupt controllers are described in Paragraph 2.5
2-1
r--INTERRUPT CONTROL ~ E1~
IR07~----------.---,-r----------~~---------------------,
GROUP 2
IRO 6 .....- - - - - , - - . - + i IRO 5 '-,----.-.--~
IRO BUFFER
INTERRUPT IR04~----------ri-t-t1-________~~~------------------~
~r--~
~~~C8~~~O
r-::)
BIAKI L
BINIT L
~~~
r-________~6~ __
~
I--
DC003
_
~
GINT
~: ~
I RO
A14
BUFFER
RIP El
"A'--_ _ _ _ _ _~
r
AI/O
IRQ _.,
SELO _ WRTCSRA _
USER RPl Y A
~-=-
A
.......,._....-;.,RI;;-P_E;;,O::.-r· "
1--(-A-N-2)----B-IA-K-O-L---tOf (AT2)
.~
....
~_(A--L2-)---_B-IR-Q-4_L~ (AMI)
~ •.Wll
CONTROLLER
CSRA
y
)
DRVllJ ROY A DRV l1J RPL Y A
r-------....._U_S_E_R_R_o_Y_B_ _--I
...
CSRB REGISTER .....
PORT
SELECT
~~L._~o_NN_DT_PR_Oo_RL_T..rl • LATCH
.. "
SEL 0
....
DRV11J RPLY B
CONTROL
lDAL lines or through the 4 USER RPL Y signals and the A I/O < I! :0> lines. The DR V 11-J cannot process interrupt requests until its interrupt control logic is enabled by the processor. The processor enables the DRY Il-J by setting the interrupt enable bit 9 of CS RA. The sequence of DRY I1-J and user device signals during an interrupt operation is shown in Figure 4-6.
4-9
DRV11-J
USER DEVICE
*REQUEST DATA • ASSERTS DRV11J ROY • DISABLES TRISTATE DATA BUFFER OUTPUTS
----~
.--
ACCEPTS DATA • SETS IRR BIT AND GROUP INTERRUPT • AN IRQ IS GENERATED IF IE IS SET • ASSERTS DRV11J RPL Y WHEN INPUT DATA BUFFER IS READ (DATA ACCEPTED)
~
--.... SEND DATA
• PLACES DATA ON I/O BUS ____ • ASSERTS USER RPL Y ___ --(DATA AVAILABLE)
-- --- --
--.... DATA ACCEPTED
INPUT COMPLETE • NEGATES DRVllJ RPL Y * NEGATES DRV11J ROY
----.. --..
• DEVICE RECEIVES DRV11J RPLY ___ • NEGATES USER RPL Y
- - . . * INPUT COMPLETE • REMOVES DATA FROM I/O BUS
NOTES IF THE USER DEVICE IS INCAPABLE OF EXECUTING THE INPUT FUNCTION PROTOCOL, DATA TRANSFER IS DEPENDENT UPON PERIODIC READING OF THE INPUT BUFFER, WITH THE DRV11-J IN AN INPUT MODE. (DIR BIT CLEARED) * THESE STEPS ARE ON L Y REQUI RED WHEN I/O MODES ARE SWITCHED FROM INPUT TO OUTPUT OR OUTPUT TO INPUT. IF MODES ARE NOT SWITCHED, THE USER DEVICE SENDS DATA AND THE DRVll-J ACCEPTS THE DATA TO COMPLETE THE DATA TRANSFER. MR-43151
Figure 4-4
Jnpui Data Transfer SC4uence
4-10
DRVll·J
USER DEVICE
·OUTPUT DATA REQUEST
-- -- --- --
·OUTPUT DATA
~
• OUTPUTS DATA ON I/O BUS • ASSERTS DRV11J RPL Y (DATA AVAILABLE)
__
~
• DEVIC;::E ASSERTS USER ROY
ACCEPT DATA • DEVICE ASSERTS USER RPLY (DATA ACCEPTED)
DATA ACCEPTED • SETS IRR BIT AND GROUP INTERRUPT • AN IRQ IS GENERATED IF IE IS SET. • NEGATES DRVl 1J RPL Y
___ __
--
~
OUTPUT COMPLETE • NEGATES USER RPL Y • NEGATES USER ROY
• OUTPUT COMPLETE • REMOVES DATA FROM I/O BUS
NOTES IF THE USER DEVICE IS INCAPABLE OF PERFORMING THE OUTPUT FUNCTION PROTOCOL, THEN DATA TRANSFERS ARE DEPENDENT ON PERIODICALLY WRITING THE OUTPUT DATA BUFFER WHILE THE USER ROY SIGNAL IS HELD ASSERTED (GND) WITH THE DRV11·J IN AN OUTPUT MODE. (D!R B!T SET) • THESE STEPS ARE ONLY REQUIRED IF MODES ARE SWITCHED BETWEEN INPUT AND OUTPUT OR OUTPUT AND INPUT. IF MODES ARE NOT SWITCHED, THE DRVll-J SENDS THE DATA AND THE USER DEVICE ACCEPTS THE DATA TO COMPLETE THE DATA TRANSFER. MR...:J52
Figure 4-5
Output Data Transfer Sequence
4-11
DRV11-J
USER DEVICE
ENABLE INPUT ·ASSERT DRVllJ ROY
---- ---
~
-........ ·ENABLE DATA
__
~
__ • PLACE DATA ON A I/O' BUS
ENABLE INTERRUPT • ENABLE INTERRUPT CONTROL
~
"""'"-
"""'"-........ REQUEST INTERRUPT
____ ---~
INTERRUPT • ASSERT GROUP INTERRUPT AND IRQ IF IE IS SET • ASSERT DRV11J RPL Y WHEN INPUT BUFFER IS READ ___
---
"""'"-
.-- • CREATE AN INACTIVE TO ACTIVE TRANSITION ON A I/O OR USER RPLY
-........ INTERRUPT DONE • RECEIVES DRV11J RPL Y
NOTE • THESE STEPS ARE NOT REQUIRED IF MODES ARE NOT CHANGING FROM OUTPUT TO INPUT. MR·4354
Figure 4-6
Interrupt Sequence
4-12
CHAPTER 5 PROGRAMl\tlING EXAl\;lPLES 5.1
GENERAL DESCRIPTION
The DR V II-J may be used in systems where the data is transferred to or from the user device under program control, or in those using interrupt-driven service routines. Programmed data transfers may be performed with or without the protocol control signals (handshaking), depending on the system's complexity. The simplest of system applications may not require the handshaking signals, whereas more complicated system applications require handshaking signals to synchronize the processor with the user device. The following three programming examples illustrate how the DR V II-J may be programmed to operate in program-controlled data transfer systems without handshaking and with, and in interrupt-driven systems. 5.2
PROGRA\1\1ED DATA TRANSFER WITHOUT HANDSHAKING
In the simplest system applications. input and output data transfers may be performed under program control by reading and writing the data buffer registers (DBRA, DBRB, DBRC and DBRD). Data can be transferred on a bit-by-bit basis. the method used when the DRV II-J is connected to a simple user device that does not generate or interpret handshaking signals. For example. I port could monitor i 6 independent switches. if. in actuai operation. input to the DR V i i -j is aiiowed to change whiie the software is reading the buffer, erroneous data may be read. In such a case, the software can "'debounce" the line by reading the line until it gives reproducible results. The routines shown in Figure 5I illustrate the software interface to the DR V) )-J. The first routine initializes the DR V I1-J for operation. The second returns the status of 1 of 32 independent input lines that are connected to the A and B I/O pins. 5.3
PROGRAMMED DATA TRANSFER WITH HANDSHAKING
In more complicated system applications, handshaking (DR V II-J polled mode) must be used between the DR V 11-J and the user device to indicate the availability of data and to synchronize the sender and receiver so that data is not lost. For example. when the DR V II-J sends a 16-bit command to a user device. it must wait until the command is executed before it can send another. Another example is where the user device assembles 16 signals and then informs the DR V II-J that data is available. I n the programming example in Figure 5-2, the first routine initializes the DRV II-J for operation. An input routine reads data from the port A I/O lines after detecting the USER RPL Y signal with the group interrupt bit in CSRA. The output routine waits for the USER RDY signal from the user device (available in CSRB) before it outputs data on the port B I/O lines.
5-1
; Routine to initialize the DRVII-J for input without handshaking. Uses ports A and B for 32 lines of input.
1 2 3
4 5 6 7
000000 000000 000004 000010
INITDR: : 005037 005037 000207
CLR CLR RTS
164160 164164
B 9
10 11
12 13 14 15 16 17 IB 19 20 21 22 23 24 25 26 27 2B 29 30
, 000012 000012 000014 000020 000022 000024 000026 000032 000034 000036 000040
010046 0427000 177757 040016 006200 006200 016000 164162 005316 100402 006200 000774
000042 000046 000050
042700 005726 000207
@tCSRA @tCSRB
initialize for input initialize for input return to caller
PC
Routine to check the status of one of the 32 input lines: The routine expects a line number ,from a to 31 in RD. It returns the state of the li~e (0 or 1) in RO.
RDLINE::
5$:
177776
10$:
000001
MOV BIC BIC ASR ASR MOV DEC BMI ASR BR
RO, -(SP) 1177757, RO RO, (SP) RO RO DBRA(RO), RO (SP) 10$ RO 5$
save the line number clear all but port flag clear all but -line in port- bits form offset from DBRA
BIC TST RTS
1177776, RO (SP) +
remove the other bits pop the saved !ine number and return to the caller
PC
read the appropriate buffer register shift the bits in RO until the right one is in bit
.END
SYMBOL Ti\B LE BASE CSRA CSRB
164160 164160 • 164164
CSRC CSRD
164170 '" 164174
Figure 5-1
DBRA DBRB
164162 164166
DBRC DBRD
164172 164176
INITDR RDLINE
Example of a Programmed Data Transfer without Handshaking
5-2
OOOOOORG 000012RG
a
Initialize the DRVII-J for programmed rio with handshaking. Set up to read from port A, write to port B.
1
2
3
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
000000 000000 000002 000006 000014 000020 000022 000026 000032 000036 000040
NITDR: : 010046 005037 012737 012700 105010 112710 112710 112710 012600 000207
164160 000400 164170
MOV CLR 164164
MOV
MOV CLRB MOVB MOVB MOVB MOV RTS
000054 000055 000204
RO. - (SP) @,CSRA 1400. @t CSR8 'CSRC, RO (RO) 154, (RO) '55, (RO) '204, (RO) (SP)+, RoPC
Routine to wait for caller in RO.
000042 000042 000046 000050
105737 100775 112737
164170
000056 000062
013700 000207
164162
000114
164170
RDPORT: : 10$: TSTB BMI MOVR MOV RTS
dat~
save RO clear DIR, ~~~
available
@,CSRC 10$ 1114, @,CSRC @,DBRA, RO PC
reset group 1 interrupt control
CSRB DrR for output
RO points to CSRC reset group 2 interrupt control clear g(OUP 2 IMR bit 4 (user reply A) clear group 2 IMR bit 5 (user reply B) set group 2 polled m0de restore saved RO return to caller VI'
pert A and
r~turn
the data .... ..., the
wait for group 2 -interruptclear group 2 IRR bit 4 so we can detect user reply A again G get DBRA ; and return to caller
Routine to send data passed by the caller in RO to port B and wait for it to be accepted by the user device. 000064 000064 000070 000074 000076 000104
WTPORT:: 010037 105737 100775 112737 000207
164166 164170 000 ll5
10$: 164170
MOV TSTB 8MI MOVB RTS
RO, @JDBRB @lCSRC 10$ '115, @,CSRC PC
put data into DBRB wait for group 2 event (data accepted) clear group 1 IRR bit 5 return to the caller
.END
000001
SAMPLE TABLE BASE CSRA CSRB
=
164160 164160 164164
CSRC CSRD DBRA
164170 164174 164162
Figure 5-2
DBRB DBRC
164166 164172
OBRO INITOR
=
164176 OOOOOORG
ROPORT WTPORT
000042RG 000064RG
Example of a Programmed Data Transfer with Handshaking
5.4 INTERRLPT-DRIVEN TRANSFER I n systems where the number of devices and/or the complexity of service increases. the DR V II-J may be used to enhance processor throughput and response time by eliminating the need for a polling program. In such applications, the DRVII-J can be initialized to interrupt the processor when the user device has accepted data (output) or when it has data available (input). The following two programs output data from port A (see Figure 5-3) and input data from port C (see Figure 5-4) under interrupt control. The program in Figure 5-3 initializes the DR V II-J to interrupt on USER R PLY A (output) and the program in Figure 5-4 initializes the DRV II-J to interrupt on USER R PLY C (input). The DR V II-J vector address memory is loaded with the vector address and the appropriate group 2 interrupt line enabled. The output program will then force an interrupt to occur by setting the group 2 port .\ I R R bit 4. This starts the interrupt service routine. which runs in parallel w'ith the main program. The programs perform unrelated functions while input/output is proceeding asynchronously. The programs then wait for a done flag. which is set by the interrupt service routines to indicate that the input loutput transfer is completed.
5-3
Program to send 256 words of data to DRVI1-J port A under interrupt control.
1 2 3
Set up DRVll-J vector at an unused location (location 400)
4 5
.ASECT
6 000000 7
8 9
10 000400 11 000402 12 13 000000
000400
=
001110' 000340
WTINT 340
this is the 256 word output buffer fill buffer with ascending numbers for test
OBUS:
000000
CaNT = 0 .REPT 256. .WORD CaNT CaNT = CONT+1 .ENDR
000000 000400
OPNTR: OFLAG:
001000 001002
next word pointer output done flag
.BLKW .BLKW
START:
001004 001004
012737
001400
001012 001016 001020 001024 001032
012700 105010 112710 112737 112737 112710 112710 112737 012767 005067 112710 112710
33 34 001040
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
interrupt is vectored to location WTINT at priority level 7 (interrupts disabled)
• PSECT
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
400
001044 001050 001056 001064 001070 001074
MOV
114 0 0, @'CSRA
164170
MOV
000344 000100 000241
164174 164160
MOVB MOVB MOVB
'CSRC, RO CLRB (RO) '344, (RO) 1100, @,CSRD 1241, @ICSRA
000241 000300 000020 164174 000000' 177714 177712 000054 000134
MOVB MOVB MOVB MOV CLR MOVB MOVB
1241, (RO) 1300, (RO) 120, @ICSRD 'OBUF, OPNTR OF LAG 154, (RO) 1134, (RO)
164160
set port A four output, enable interrupts, and reset group 1 interrupt controller RO points to CSRC reset group 2 interrupt controller preselect vector address memory (line 4) load vector of 400 arm group 1 with master maks bit this will enable group 2 arm group 2 with master mask bit preselect ACR for writing set ACR to clear line 4 (user reply A) initialize output pointer and done fl ag clear group 2 IMR bit 4 (user reply A) set group 2 IRR bit 4 (cause an interrupt) to get things started)
NOW, the CPU can be used for other things while the data is being sent. Some time later ..• 001100 001:04 001106
005767 001775 000000
177676
10$:
TST BEQ HALT
OF LAG 10$
; The following 001110 0011Jo 001116 001124 001126 001134 001142
112737 026727 001407 017737 062767 000002
000114 177656
164170 001000'
177646 000002
164162 177636
001144 001150
005267 000002
177632
wait for output complete
is the interrupt service routine.
WTINT:
001004'
MOVB CMP BEQ MOV ADD RTI
1114, @ICSRC OPNTR, ,OBUF+5l2. 10$ @OPNTR, @'DBRA '2, OPNTR
clear group 2 IRR bit 4 (REPLY A) ; sent all words in buffer? if so, we're done else send out next word point to following word return from interrupt
10$: RTI
INC
OFLAG
signal output complete return from interrupt
.END
START
SYMBOL TABLE BASE CONT CSRA
164160 000400 164160
CSRB CSRC CSRD
=
164164 164170 .. 164174
=
DBRA DBRB DBRC
164162
DBRD OBUF OF LAG
= 164166
,. 164172
164176 OOOOOOR 001002R
OPNTR START WTINT
OOlOOOR 001004R OOlllOR "''' .. 739
Figtlre 5-)
Example of an !nterrupt-Dr!ven Output Program
5-4
Program to read 256 words of data from ORVI1-J port C under interrupt control.
2 3 4 5 6 000000 7
Set up DRVII-J vector at an unused location (location 400). .ASECT = 400
000400
9 ~O
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
000400 000402
.PSECT
000000 rBUS: I PNTR: IFLAG;
000000 001000 001002 012737
001000
001012 001016
012700 005010
164170
001020 001024 001032
112710 112737 112737
000346 000100 000241
001040 001044 001050 001056 33 001064 34 001070 35 36 37 38 39 40 41 42 001074
112710 112710 112737 012767 005067 112710
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
001102
. BLKW . B LKW
256.
256 word input buffer next empty word pointer
input done flag
START:
001004 001004
43 001100
interrupt is vectored ~o location HDINT at pri?rity level 7 (interrupts disabled)
HOINT 340
001104' 000340
MOV
ilOOO, @'CSRA
MOV CLR
ICSRC, RO (RO)
164174 164160
MOVB MOVB MOVB
'346, (RO) tl 00, @'CSRO 1241, @'CSRA
000241 000300 164174 000100 000000' 177714 177712 000056
MOVB MOVB MOVB MOV CLR MOVB
1241, (RO) '300, (RO) 1100, @ICSRD iIBUF, IPNTR IFLAG '56, (RO)
164160
Now,
reset group 1 interrupt controller, enable DRVll-J interrupts RO points to CSRC set port C for input, reset group 2 interrupt controller preselect vector address memory (line 6) load vector of 400 arm group 1 with master mask bit this will enable group 2 arm group 2 with master mask bit preselect ACR for writing set ACR to clear line 6 (user reply C) initialize input pointer and done flag clear group 2 IMR bit 6 (user reply C) interrupts will now be generated on data received from port C
the CPU can be used for other things while the data is being received.
Some time later ...
005767 001775 000000
177702
TST
.Lv;;>
IFLAG 10$
BEQ
i
.ait for input finished
HALT i
The following
001104 001112 001120 001126 001134 001136
112737 013777 062767 026727 001005 112737
000116 164172 000002 177646
164170 RDINT: 177660 177652 001000'
000036
164170
001144 001150
005267 000002
177632
is the interrupt service routine.
MOVB MOV ADD CMP BNE MOVB
1116, @ICSRC @IDBRC, @rPNTR 12, IPNTR IPNTR, IlBUF+512. 10$ 136, @ICSRC
INC
IFLAG
10$:
001004'
clear group 2 IRR bit 6 (REPLY C) get the word just received bump buffer pointer ; buffer full? branch if buffer not full we're done. Set group 2 IMR bit 6 inter rupt) signal input complete
return from interrupt . END
STAR'!'
SYMBOL TABLE BASE CSRA CSRB
164160 164160 164164
CSHC CSRO DBRA
164170 164174 164162
DBRB DBRC DBRD
Figure 5-4
Exampie of an interrupt-Drtven Input Program
164166 164172 164176
IBUF IFLAG IPNTR
5-5
DOOOOOR 001002R OOlOOOR
RDrNT START
aCll04R OOl004R
(disable
CHAPTER 6 OPTIC ISOLATOR INTERFACE EXAl\1PLE GENERAL DESCRIPTION The DR V II-J can be used for industrial machine control. process control, monitoring applications. etc. When the module is used in industrial applications, the computer system must often operate in a hostile electrical environment. The DR V II-J may have to control or monitor components such as lamps. motors. relays and switches. all of which generate electrical noise. In such an environment. interfacing the DRVII-J to the user device(s) through optically coupled isolators may be necessary. Optic isolators are used to isolate electrically and/ or convert signal levels between the user device(s) and the DRV! I-J latched output drivers in output mode, or the unlatched Schmitt trigger buffers in input mode. The simplified schematic Figure 6-1 shows how the optic isolators may be connected to the DRV) I-J for data input and output transfers. The choice of an appropriate optic isolator or optic isolator module depends upon the requirements of the specific application.
6-1
ORV11J INPUT MODE ONLY
ORV11 J ORV11·J CONN INPUTS (X) 110
(X) 10· 15:0>
USER CONN. USER INPUT
(X) I/O
OPTIC ISOLATOR
• •
ORVllJ ROY (XI-+-++---\ +5 V
ORVllJ RPLY IXI-t+-+--"""
tV OPTIONAL RESISTOR
USER ROY (Xl \---+~4--..L.-.----- (ALWAYS HIGH)
+5 V
\--+.-t--------
USER RPL Y (X)
CABLE (BCOSWI ORVll·J OUTPUT MODE ONL Y
TSO' 150>
ORV11J OUTPUTS (X)IIO
D
ORV11-J CONN
USER CONN r0-
USER (X) 110
C
I
LS374 WRT DB IXI
~
>CK
OIR IX)
+5 V
( I
J.
'5V~
USER ROY (XI
( I
"'~ OPTIC ISOLATOR
-b
(
ORV11J ROY (X)
I
ORV11J RPLY (X)
l I
USER RPLY (X)
(
USER RPLY (X)
I
CAB LE (BCOSWI
'-
~WTE
IXI
-~
A. B, C, OR 0
MA OJ59
Figure 6-1
Example of an Optic Isolator Interface
6-2
Reader's Comments
DRVII-J Parallel Line Interface User's Guide
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