EK-RQDX l-UG-OO 1
RQDXl Controller Module User's Guide
EK-RQDX l-UG-OO 1
RQOXl Contr()lIer Module IUser's Guide
Prepared by Educational Services of Digital EquipmE~nt Corporation
First Edition" January 1984
Copyright © 1984 by Digital Equipment Corporation All Rights Reserved Printed in U.S.A. The material in this document is for informational purposes and is subject to change without notice; it should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document.
Notice: This equipment generates, uses, and may emit radio frequency energy. The equipment has been type tested and found to comply with the limits for a Class A computing device pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable protection against such radio frequency interference when operated in a commercial environment. Operation ofthis equipment in a residential area may cause interference in which case the user at his own expense may be required to take measures to correct the interference. The manuscript for this book was created using aD I G ITAL Word Processing System and, via a translation program, was automatically typeset on DIGITAL's DECset Integrated Publishing System. Book production was done by Educational Services Development and Publishing in Marlboro and Bedford, MA. The following are trademarks of Digital Equipment Corporation.
mamaala
DEC DECnet DECUS DECsystem-l0 DECSYSTEM-20 DECwriter DIBOL DIGITAL EduSystem
lAS LA LETTERPRINTER 100 LETTERWRITER 100 LSI-II MASSBUS MICRO/PDP-II MINC-II OMNIBUS OS/8
PDP PDT RSTS RSX TOPS-IO TOPS-20 UNIBUS VAX VMS VT
CON1'ENTS Page
PREFACE CHAPTER 1
INTRODUCTION
1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4
DESCRIPTION .............. " .......................................... FEATURES ................. " ......................................... SPECIFICATIONS ............, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. RQDXl Disk Controller Module. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. RD51 Disk Drive ......... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. RX50 Diskette Drive ...... " . . . . . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. RQDXI-E Extender Module Option....... . ........... ...... ..........
CHAPTER 2
FUNCTIONAL DESCRIPTION
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19
INTRODUCTION ............ " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1 BLOCK DIAGRAM DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1 SHUFFLE STEP OSCILLATOR......................................... 2-3 PHASE LOCKED LOOP ...... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4 DATA RECOVERY .......... " ......................................... 2-5 SYNC MARK DETECTOR ... ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5 SERIALIZER/DESERIALIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6 MFM ENCODER/PRECOMP GrENERATOR ............................. 2-6 INTERRUPT VECTOR REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8 SA READ REGISTER, SA WRITE REGISTER, IP REGISTER. . . . . . . . . . .. 2-8 QBUS TRANSCEIVERS AND HANDSHAKE CONTROLLERS. . . . . . . . . .. 2-8 RQDXl CONTROL LOGIC ............................................. 2-10 MEMORY ADDRESS COUNTER/REGISTER ........................... 2-12 2 K X 16 RAM ......................................................... 2-12 DISK DRIVE CONTROL REGISTER AND STATUS BUFFER ............ 2-12 T-l1 RAM ADDRESS POINTER AND ALU ............................. 2-14 BIDIRECTIONAL BYTE MULTIPLEXER ............................... 2-14 8 K X 16 PROM ........................................................ 2-14 QBUS DMA POINTER AND ALU ...................................... 2-14
CHAPTER 3
CONFIGURATION AND INSTALLATION
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.7.1 3.7.2
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. DEVICE ADDRESS SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. LOGICAL UNIT NUMBER SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. INTERRUPT VECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. INTERRUPT REQUEST LEVEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. RQDXl CONTROLLER MODULE INSTALLATION .................... RQDXI-E EXTENDER MODULE OPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . .. RQDXI-E Extender Module Jumper Configuration. . . . . . . . .. . . . . . . . . . . .. RQDXI-E Extender Module Installation. . . . . . ... .. . . . . . . . . . . . . .. . . . . ..
iii
1-1 1-2 1-2 1-2 1-3 1-4 1-6
3-1 3-2 3-3 3-4 3-4 3-4 3-4 3-5 3-6
CONTENTS (Cont) Page CHAPTER 4
REGISTERS AND COMMANDS
4.1 4.2 4.2.1 4.2.2 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. REGISTERS ........................................................... Initialize and Poll Register (IP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Status and Address Register (SA) ..............................' . . . . . .. MASS STORAGE CONTROL PROTOCOL (MSCP) ............... " . . . . . .. MSCP Commands .......................................... " . . . . . .. MSCP Status Codes ......................................... " .. '. . . .. DIAGNOSTICS AND UTILITIES PROTOCOL (DUP) ............ " . . . . . .. DUP Commands ........................................... " ....... DUP Responses ............................................ " .......
CHAPTERS
ERROR DETECTION
5.1 5.2 5.3
INTRODUCTION ........................................ " ..... '. . . . . . .. 5-1 DIAGNOSTIC LED ERROR DISPLAYS ......................... '. . . . . . .. 5-1 DIAGNOSTIC SOFTWARE .................................... '. . . . . . .. 5-3
CHAPTER 6
DISK DRIVES
6.1 6.2 6.2.1 6.2.2 6.3
INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. RD51 DISK DRIVE .................................................... RD51 Disk Drive Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Formatting the RD51 Disk Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. RX50 DISKETTE DRIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
APPENDIX A
RQDXl CONTROLLER MODULE BACKPLANE PIN ASSIGNM:ENTS
APPENDIX B
RQDXl CONTROLLER MODULE CABLE SIGNALS
APPENDIX C
DISK DRIVE CABLE CONNECTOR PIN ASSIGNMENTS
C.1 C.2
RD51 DISK DRIVE CONNECTOR PIN ASSIGNMENTS. . . . . . . . . . . . . . . .. C-l RX50 DISKETTE DRIVE CONNECTOR PIN ASSIGNMENTS ....' . . . . . .. C-3
iv
4-1 4-1 4-1 4-1 4-2 4-3 4-4 4-5 4-5 4-6
6-1 6-1 6-2 6-3 6-4
FIG1JRES Figure No. 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 3-1 3-2 3-3 3-4 3-5 3-6 4-1 5-1 6-1 6-2 6-3 6-4 6-5 A-I
Title
Page
RQDXl Controller Module Functional Block Diagram ....................... 2-2 Shuffle Step Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3 Phase Locked Loop Logic ................................................ 2-4 Data Recovery and Sync Mark D(:tector Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5 Serializer/Deserializer and MFM Encoder/Precomp Generator Logic . . . . . . . . . .. 2-7 Interrupt Vector Register, SA Regiisters and QBus Interface Logic. . . . . . . . . . . . . .. 2-9 T-ll, RAM and ROM Logic .............................................. 2-10 Main High-Speed Controller Architecture ................................... 2-11 Disk Drive Control Register and Status Buffer ............................... 2-13 RQDXl Controller Module Jumpier and LED Locations ...................... 3-1 RQDXl Address Selection Jump(~r Format .. . . . . . . . . . . . . . ... . . .. . . . . . . . . . .. 3-2 RQDXl Logical Unit Number Jumper Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3 RQDXl MICRO/PDP-II Signal Distribution Connections. . . . . . . . . . . . . . . . . . .. 3-4 RQDXI-E Extender Module Jumper Locations .............................. 3-5 RQDXI-E Extender Module Connections .................................. 3-6 Memory "Communications Area" Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2 Diagnostic LED Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1 RD51 Disk Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1 RD51 Disk Drive Read/Write Printed Circuit Board. . . . . . . . . . . . . . . . . . . . . . . . .. 6-2 RD51 Disk Drive Head Positioner Flag ..................................... 6-3 RD51 Serial "Number Label Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-4 RX50 Diskette Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-5 Quad Module Contact Finger Identification ................................. A-I
TAB:LES Table No. 1-1 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 6-1 A-I B-1 C-l C-2 C-3 C-4 C-5
Title RQDXl Controller Module Configurations.. . . . ... . . . . . . . . . .. . . . . . . . . . . . . . .. RQDXl Standard Address Jumper Configuration... .... . . . . . . . . . . . . . . . . .. . .. RQDXl Standard Logical Unit Number Jumper Configuration. . . . . . . . . . . . .. . .. RQDXI-E Extender Module Jumper Configuration .......................... MSCP Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. MSCP Status Code Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. DUP Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Diagnostic LED Error Displays ........................................... XXDP+ Diagnostic Programs ............................................ DIP Shunt Jumper Configuration .......................................... RQDXl Controller Module Backplane Pin Assignments ...................... Jl Connector Signals ..................................................... . RD51 Disk Drive J 1 Signal Conm:ctor Pin Assignments .. . . . . . . . . . . . . . . . . . . .. RD51 Disk Drive J2 Signal Conm:ctor Pin Assignments . . . . . . . . . . . . . . . . . . . . .. RD51 Disk Drive J3 Power Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . .. RX50 Diskette Drive J 1 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . .. RX50 Diskette Drive J3 Power Connector Pin Assignments . . . . . . . . . . . . . . . . . ..
v
Page 1-1 3-2 3-3 3-5 4-3 4-4 4-5 5-2 5-3 6-2 A-2 B-1 C-l C-2 C-2 C-3 C-3
PREFACE
This user's guide provides information on the configuration, installation, and operation of the RQDX I disk drive controller module, the associated disks (the RD51 Winchester fixed disk drive and the RX50 diskette drive), and the RQDXI-E extender module option. Chapter I provides environmental and functional specifications for the RQDXI controller module, the RD51 fixed disk drive, the RX50 diskette drive, and the RQDX I-E extender module option. Chapter 2 gives a functional description of the RQDX I controller module. Chapter 3 presents configuration and installation information for the RQDX I controller module and the RQDX I-E extender module option. Chapter 4 describes the programmable registers that are LSI-II bus addressable on the RQDX I controller module. Mass storage control protocol (MSCP) and diagnostics and utilities protocol (DUP) are also briefly described. Chapter 5 provides testing and error detection information. Chapter 6 presents installation and operation information for the RD51 fixed disk drive and the RX50 diskette drive. RELATED DOCUMENTATION The following documents provide additional information and may be of interest to RQDXI controller module users. Document Title
Document Number
RQDX I Field Maintenance Print Set UDA50 Programmer's Documentation Kit
MP-OI731-01 QP-905-GZ
In addition, users may refer to documentation for the specific system in which the RQDXI controller module is installed.
vii
CHAPTER 1 INTRODUCTION
1.1 DESCRIPTION The RQDX 1 disk drive controller module interfaces, the RD5I disk and/or RX50 diskette drives to any quad- or hex-size backplane that uses a 16-, 18-, or 22-bit LSI-II bus. The backplane must be in a mounting box (such as a BA23) that provides a control panel and a signal distribution panel. A single RQDX 1 module controls anyone of the configurations listed in Table 1-1. Table 1-1 Configuration
RQDXl Controller Module Configurations Logical Disk Drive Numbers
Physical Disk Drives One RD51, one RX50
Unit 0 = RD51 Unit 1, 2 = RX50
2
Two RX50s
Unit 0, 1 = RX50 Unit 2, 3 = RX50
3*
Two RD51s One RX50
Unit 0 = RD51 Unit 1 = RD51 Unit 2, 3 = RX50
4*
Two RD51s
Unit 0 = RD51 Unit 1 = RD51
5
One RX50
Unit 0, 1 = RX50
6
One RD51
Unit 0 = RD51
*
These configurations require the use of the optional RQDX J-E extender module. Refer to Paragraph 3.7 for additional RQDX J-E information.
The RD51 disk drive is a random access storage device, which uses two non removable 133.4 mm (5.25 inch) disks as storage media. The RD51 disk drive has a total formatted storage capacity of II megabytes. The RX50 diskette drive is a random access storage device, which uses two single-sided 133.4 mm (5.25 inch) RX50K diskettes. The total storage capacity of the RX50 diskette drive is 800 kilobytes of formatted data. The RQDX l-E extender module option provides cable connection to a single disk or diskette that is mounted externally from the MICRO/PDP-II (BA23) mounting box.
1-1
1.2 FEATURES The RQDX I controller module has the following features. •
Single quad-size module.
•
Supports DMA data transfers in 16-, 18-, or 22-bit addressing modes.
•
Supports block mode transfers with MSVII-P memories.
•
Supports 22-bit addressing on an LSI-II bus.
•
Memory parity error abort feature for use with memories that have a parity option.
•
Requires no jumper/switch reconfiguration when adding or removing RDSI or RXSO drives.
1.3 SPECIFICATIONS 1.3.1
RQDXl Disk Controller Module
Module
I quad-size module, M8639
Size
Height: 26.S6 cm (10.46 in) Width: 1.27 cm (O.S in) Length: 22.70 cm (8.94 in)
Power Requirements
+S Vdc ±S% at 6.4 A (typical) 8.0 A (maximum) +12 Vdc ±S% at 7.3 rnA (typical) 10 rnA (maximum)
Bus Loads AC Bus Loads DC Bus Loads
2.S I
Addressing Modes
16-, 18-, and 22-bit (determined by user)
Limitations
The RQDX I will not fit in the dual-height LSI-II mini-series H9281 backplane.
Drives Per Controller
Up to four logical units, no more than two RDSI disk drives
LSI-II Bus-Addressable Registers
2
Base Device Address (Standard)
Addressing Mode
Address (Octal)
16-bit 18-bit 22-bit
1721S0 7721S0 177721S0
1-2
Vector
Software selectable (I\rormally set at 154)
Data Transfer Rate
800 ns/word (peak) controller to host
Environmental Specifications Temperature Storage Operating
-40°C to 66°C (-40°F to 150°F) 5°C to 50°C (41°F to 122°F)
Relative Humidity Storage Operating
10% to 95%, noncondensing 10% to 95%, non condensing
Altitude Storage Operating
9.1 km (30,000 ft) maximum 2.4 km (8,000 ft) maximum
Airflow Operating up to 50°C
t .3.2
Maximum temperature rise across module must not exceed 20°C (68°F) input to output.
RD5 t Disk Drive
Storage Type Medium
Winchester fixed disk
Recording Surfaces
4 data surfaces
Magnetic Heads
4 read/write heads
Recording Method
Modified frequency modulation (MFM)
Performance Specifications Recording Capacity (Formatted) Bytes Per Sector
512 bytes
Sectors Per Track
18 sectors (track size) Each sector has a logical block number (LBN)
Tracks Per Group
4 tracks (group size)
Groups Per Cylinder
3 groups (cylinder size)
Cylinders Per Unit
100 cylinders
Total Cylinders Per Unit
102 cylinders *
Total Bytes Per U ni t
11.059 M bytes 5,000,000 bits/s (625 K bytes/s)
Transfer Rate Access Time (Buffered Seek, Including Settling) Average
85 ms
Maximum
205 ms
A verage Latency
8.33 ms
Functional Specifications Rotational Speed
3,600 r/min (±1 %)
Recording Density
9,074 bits/in (maximum)
Track Density
345 tracks/in
Environmental Specifications Ambient Temperature Relative Humidity
20% to 80% noncondensing
Maximum Wet Bulb 1.3.3
RXSO Diskette Drive
Storage Type Medium
Diskette
Recording Surfaces
2 data surfaces
Magnetic Heads
2 read/write heads
Recording Method
Modified frequency modulation (MFM)
* Cylinders
100 and 101 are assigned as follows.
Cylinder 100, Group 0: Cylinder 100, Groups I, 2: Cylinder 101, Groups 0, I: Cylinder 101, Group 2:
Replacement and caching table (RCT) Format control table (FCT) Replacement block numbers (RBNs) Diagnostic block numbers (DBNs) Reserved
1-4
Performance Specifications Recording Capacity (Formatted) Bytes Per Sector
512 bytes
Sectors Per Track
10 sectors (track size) Each sector has a logical block number (LBN).
Tracks Per Group
5 tracks (group size)
Groups Per Cylinder
16 groups (cylinder size)
Cylinders Per Surface
1 cylinder
Bytes Per Surface
404,480 bytes
Surfaces Per Unit
2 surfaces (2 diskettes)
Bytes Per Unit
808,960 bytes
Transfer Rate
250,000 bits/s (31.25 K bytes/s)
Access Time Track to Track
Minimum
Typical
Maximum
6 ms
Head Settling Time
30 ms
Head Load Time
30 ms
Rotational Latency
100 ms
Random Access
264 ms 250 ms
Drive Motor Start Functional Specifications Rotational Speed
300 r/min (±1.5%)
Recording Density
5,576 bits/in (maximum)
Track Density
96 tracks/in
Environmental Specifications Ambient Temperature Relative Humidity
200 ms
20% to 80% non condensing
Maximum Wet Bulb 1-5
1.3.4
RQDXI-E Extender Module Option
Module
1 dual-size module, M7 S12
Size
Height: 13.2 cm (S.2 in) Width: 1.27 cm (O.S in) Length: 22.8 cm (8.9 in)
Power Requirements
+S Vdc at O.S A (typical) 0.6 A (maximum)
Bus Loads AC Bus Loads DC Bus Loads
o o
Provides signal distribution to a single disk or diskette drive
Limitations
Cannot be used on the PDP-II /23 Plus Environmental Specifications Temperature Storage Operating
-40°C to 66°C (-40°F to IS0°F) SoC to 60°C (41°F to 140°F)
Relative Humidity Storage Operating
10% to 9S%, noncondensing 10% to 9S%, noncondensing
Altitude Storage Operating
9.1 km (30,000 ft) maximum 2.4 km (8,000 ft) maximum
Airflow Operating up to SO°C
Maximum temperature rise across module must not exceed 20°C (68°F) input to output.
1-6
CHAPTER 2 FUNCTIONAL DESCRIPTION
2.1 INTRODUCTION The RQDX I controller module interfaces the RD51 disk drive and/or RX50 diskette drives to a 16-, 18-, or 22-bit LSI-II bus. One RQDXI controller module can support up to four logical units in any combination of RD51 and RX50 drives (up to two RD51 drives per RQDX I controller module). The RQDX I controller module (M8639) has the LSI-II bus transceivers and decoders, programmable registers, controller timing and sequence logic, and the data formatting circuits necessary to read and write on lthe RD51 disk media and/or the RX50 diskette media. :!.2 BLOCK DIAGRAM DESCRIPTION The main functional subsections of the RQDX I module are shown on the block diagram in Figure 2-1. The block diagram illustrates the basic architecture and the data path relationships of the major subsections. The RQDX I controller module is a bus-oriented system controlled by a system control function shared by the T-II chip and the main high-speed controller. The major subsections of the RQDX I are as follows. • • • • • • • • • • • • • • • • •
Shuffle step oscillator Phase locked loop Data recovery Sync mark detector Serializer/ deserializer MFM encoder/precomp generator Interrupt vector register SA read/write registers, IP register QBus transceivers and handshake controlle:r RQDX 1 control logic: T-II chip and main high-speed controller Memory address counter/register 2 K X 16 RAM Disk drive control register and status buffer T -I I RAM address pointer and arithmetic logic unit (ALU) Bidirectional byte multiplexer 8 K X 16 PROM QBus DMA pointer and ALU
2-1
Cl-BUS
Q-BUS CONTROL SIGNALS
Q-BUS TRANSCEIVER AND SATELLITE HANDSHAKE CONTROLLERS
GO T11 MICROPROCESSOR (7_5 MHZ, 16 BIT)
REQTlIDMA Tll DMAACK
1------.1 TAKE BUS
MAIN HIGH SPEED CONTROLLER (100 nslSTATE)
.. CONTROL ..
tv I tv
SE RIALIZE R/DESER IALIZER
NRZWRITE DATA
2K x 16 STATIC RAM
MFM ENCODER AND PRECOMPENSATION CONTROLLER
8K x 16 EPROM
DEVICE CTl BLOCK
--------SECTOR BUFFER WRITE DATA
DISK DRIVE
Figure 2-1
RQDX 1 Controller Module Functional Block Diagram
INIT TIMEUP
PROGRAMMABLE TIMER
2.3 SHUFFLE STEP OSCILLATOR The shuffle step oscillator (Figure 2-2) is a system of two matched 10 MHz oscillators, a small asynchronous oscillator controller, and a read data delay equalizer. When one of the oscillators is generating a raw read clock signal for the phase locked loop (PLL), the other oscillator is in stand-by. At each raw read data pulse, the active oscillator is commanded to turn off and the stand-by oscillator is commanded to become active. This causes the oscillators to "shuffle" to keep in step with the RAW read data. The read data delay equalizer section delays the RAW read data to compensate for the short amount of time that it takes to shuffle the oscillators.
' £
3
SELFLOPY(H) SELWINCH1(H)
B A
2
1
0
8 TO 1 MUX (74LS151) RSTRDF/F(L)
RD F/F
INITDVDR(L)
DLQRDDATA(H)
10MRAWOSC(H)
Figure 2-2
Shufflle Step Oscillator
2-3
2.4
PHASE LOCKED LOOP
The phase locked loop (PLL) logic is shown in Figure 2-3. The PLL is a dual-channel, single··mode system. Dual channel provides one channel for the RX50 diskette drive(s} and one channel for the RD51 disk drive(s}. The function of the PLL logic is to provide the "flywheel" effect for the shuffle step oscillator output, thus integrating the effects of the "pulse drift" in the RAW read data. The output of the PLL is fed into a counter which generates two data recovery window signals. These "windows" are generated in a way to center the read data pulses. (At any given time the data will be framed by one of these windows.) The proper data framing window is selected automatically by the sync mark detector.
REFCLK(H)
PHASE DETECTOR (74574 74564) ~
")
PMPUP(L)
PMPDWN(L)
~
o
..
ACTIVE FILTER AND CHARGE PUMP
~~arjE;r :
x
>= CI..
(LF347)
o..J U.
..J W
V)
E
VC
I I
E
DUAL VCO : WINNY
FLOPPY
I
DLQRDDATA(H)
!
VC
(74L5626)
()
:i
10MRAW05C(H)
(5
u
20MHZVCO(L)
> N
500KHZ05C(H)
:c
! 1
~ 0
1
~
0
()
()
1
0
2TO 1 MUX (745157)
5
5ELFLOPY(H)
~
C)
BITCELL
2XVCO(L)
~
2XVCO(H) ()
VCOOUTPUT(~~ REFCLK(H)
AWINDOW('L-J
RDDATA(H)
VCOOUTPUT(H) MR-'1290
Figure 2-3
Phase Locked Loop Logic
2-4
2.5 DATA RECOVERY The data recovery logic (Figure 2-4) consists of two single-bit, edge-triggered, double-buffered registers. The registers are cross-coupled in order to capture the read data occurring anywhere within either data framing window. Together with the phase locked loop output, an NRZ read data stream is produced. 2.6 SYNC MARK DETECTOR The sync mark detector logic (Figure 2-4) provides two functions. One, it detects the sync mark, and, two, it selects the proper stream from the data recovery logic. Both data recovery bit streams are analyzed to find the sync mark. Upon detection of the sync mark in either stream, the serializer/deserializer logic receives the desired data stream. VCOOUTPUT(H)
»z
:0 N
--,
c~~~ ! SERLSRCLK(H)
STATE REGISTEF]
OJ
Z :0 N
o
»--I
o
»--I
~
:c
I I
.J.A~~S~ ADRMRKFND(H)
SERLSRCLK "vca OUTPUT" AWINDOW MFM _ _+-' '--~"-T--+~ 'T~-~ '--__.I.1If:_---'n
o
AN RZDAT _ _ _-'
BNRZDAT MFM
........--"--~-----L-'f-"--------'
I
-.
nl.....-+-_ _ }
_:-+--....J
;- ~.,
n ___JI n
I
I
~O 0
I
1
0
BNRZDAT
~~1-'
0
I
~~
ADF:MRKFND(H)
IS LOCKED TO CELL BOUNDRYS "CLOCKS"
Al OA
in'---+---
ANRZDAT~_~~~
WHEN WINDOW
}
WHEN WINDOW IS LOCKED TO CELL CENTERS "ONES"
r-
MR-11288
Figure 2-4
Data Recovery and Sync Mark Detector Logic
2-5
2.7 SERIALIZER/DESERIALIZER The serializer /deserializer is shown in Figure 2-5 and consists of the following four parts. • • • •
A double-buffered serial in/parallel out register A double-buffered parallel in/serial out register A eRe generator/checker A high-speed finite state machine controller
The serial in/parallel out (SIPO) logic shifts the serial read data through the eRe generator and forms an 8-bit parallel byte. The byte is buffered for data transfer. The parallel in/serial out (PISO) logic receives the parallel write data, buffers it, and shifts this data serially through the eRe generator to the MFM encoder and precomp generator. This serial data becomes the write data to be sent to the disk. Both the SIPO and the PISO logic are controlled by the high-speed machine controller. 2.8 MFM ENCODER/PRECOMP GENERATOR The MFM encoder/precomp generator logic (Figure 2-5) receives the serial data to be written to the disk and performs the following operations. 1.
It generates a modified frequency modulation (MFM) data bit stream.
2.
It precompensates the MFM bit stream (for both the RD51 disk drive and the RX50 diskette drive).
3.
It generates the sync mark bit sequence on command.
2-6
HIGH SPEED CONTROLLER
1
A ~
(
...J
~
~ ;:oc ~ 8a:
tU
r NRZRDATA (H)
0
W/R BUF FLG (74LS74) R
t-
-:2J: J: ~ -0'" a: t~ ~H~ ~
~
W/RBUFFLG (H)l
~ ~ w
2
1
I
...J
t-
<-
;:
DAL(7:Q) (H)
en
rt J
L '-
-=t::.
ADRMRKFND (H)
LASTWORD (H)
I
~
LJ,eUAL RANK BYTEJ CTRL HOLD REG r-----------I~r> (2 x 74LS175)
c","'o",":
LDPISOBUF (H)
L..-_ _ _ _ _- ,
~
a: '" U
~ «o J:Ud da:U g O a: a: a:
~
:1
;;:
it
'ty' ~
I
~ ,
LUN BUFFER (l4LS240)
II
"
i~
f-
I
~~~'b~T.
n
~
q
II I I I I r::::i:L Z 1="(3): ::> z -' ~ ~ 0 o >- Q. '" a: ~ a: f- o f- f- a:
()
()
,'NTERRUPT , CONTROLLER (DCOO3 1/2 74S74)
REQVECTOR(H)
I
q c
§ :J ~+ ~a ~ ~
~ Tll
HIGH SPEED CONTROLLER
Figure 2-6
f-
I
! ~
QBUS DMA REQUEST' CONTROLLER (PAL 16LS)
I
x
,
i I
I
PIOCONTROL
TO T11 INTERRUPT Tll MEMORY MAP
g~ ~~ g~ ~~ ~~
I
~
\
7
I
I
f-
"
I
~
::::; ::::; ::::; ::::;
~
>
9
E
()
I
;;:
Q.
15
V
::::;
I
::::;
Q
(3 x xDS8641)
z z §" ~ ~ ~ ~ ~ ~
(1/2 74LS74)
(1/274LS74)
I
~
~
,
QBUS TRANSCEIVER
D~'----II--+--r-D~---+------i~ ~
::::;
() () f) ) () () ( () () ) (
LJ'---r--T--r-r~~......-r-Tl~~~----r--r-'
~---,i'r,----,--~-----"'--{I---,...;--'
~V
N \0
SA READ REG (2 x 74LS374) / \
~'" i ,
:::;
:;:
}~16
16
SA WRITE REG (2 x 74LS374)
f-
f-
~~
E
~
o
~
I
I
;;:
:;:
::::;
Interrupt Vector Register, SA Registers and QBus Interface Logic
2.12 RQDXI CONTROL LOGIC The supervisory control of the complete RQDXl controller module is a shared function between the T-ll chip and the main high-speed controller. These two devices share the internal data address blllS (DAL bus). (Refer to Figure 2-1) The T -11 chip has control over all housekeeping functions that are considered to be slow or those that require data processing. The T-ll chip is configured into the 16-bit static mode driven by a 7.5 MHz clock. The T -11 logic, along with the RAM and ROM memories, is shown in Figure 2-7.
r
HIGH SPEED CONTROLLER T·ll MEMORY MAP 200000
1
256 CSR'.
117400
REQTIIDMA(H) . - -_ _ _ _ _---1 TIIDMAACK(L)
NOT USED NOT USED
INTERRUPT REGISTER PWR UP AND DMA LDGIC
+
:J
I
~~ 2K X
\
(74LS15S)
____
W ""-
f'
-..;
"l'
-
[ \ 21
___
1~ RAM
.....,""""r-~~""--I~_(2_X~4~01... 6)....J
(74LSJO, PAL lSLS 2 x 74LS13S)
_
I
-=M::EM:::A:"::;DRH _ _ _ _ _---'
I rl
~
0
__-.,. _____
MEMORY DECODE
~
~
S lMUX
V :; ;3
~
J
4\
1~...--
~
5
l. ...--_~ll_.w..---. al
in
1.U)
:J
W
:J
0
~
g
a:i
a:i
i
16
:::;;
~
DEVICE SELECT
Figure 2-7
T -11, RAM and ROM Logic
2-10
I,......---.:Io£....~------. ~~RXO:: I
___
(2 X 27M)
~
(1/2 74LS240)
L..-_"'--~"'--_~/
~
MODE BUFFER
I
_
J
~
~
I
RAS(H)l ADDRESS LATCH (4 X 74LS163)
~
1\
j
~
CONT~OLLER
_
HIGH SPEED \
~
ASYNHOLD (74LS373)
J
7.5 MHZ XTAL OSC
~
1
-
(2 X PAL 16LS)
The main high-speed controller controls the high-speed read, write, and DMA functions to or from host memory. This controller is configured as a microprogrammed multibranch controller operating at 10 MHz. The main high-speed controller architecture is shown in Figure 2-8.
LDCOFLAG(H)
CONTROL INPUTS
~ 21
(1/274LS74) GO(HI
CLR
CONTRCLK(H)
WATCH DOG TIMER
7.5 MHZ
(74LS292) MUX1(H) ~
z
~ Cl « UJ
Cl
E a:: .....J
U
co
EN4WAY(L) FLAGO(H) NXTSTATE(H)
r I I
RESETCTL(L)
I
CONTROL OUTPUTS
Figure 2-8
T11 BUS OUTPUTS
Main High-Speed Controller Architecture
2-11
MR-11293
The 1'-11 chip sets up all disk drive control signals, initializes the timer, clears the parity error flag, and resets the shuffle step oscillator. The 1'-11 chip then sets up the device control block (DCB) with parameters for the high-speed controller, initializes the response word with Is, and then sets the GO flag in the I/O map. The high-speed controller, upon receipt of the GO signal, requests direct me:mory access to the DAL bus from the T-ll chip. Upon receipt of the TI1DMAACK signal, the controll(~r takes control of the DAL bus and begins the operation specified in the function code. Upon completion, various parameters are placed in T-l1 RAM, the controller response word is filled in (in the DCB), the GO bit is cleared, and control is returned to the T -11 chip. All high-speed controller operations must be completed within 1 second or the timer logic will terminate controller operation. 2.13 MEMORY ADDRESS COUNTER/REGISTER The memory address counter/register (shown in Figure 2-7) is used to latch the T-ll luemoryaddress during the address phase of the bus cycle. The counter function of the address register is used by the highspeed controller to form a RAM pointer which can be incremented. 2.14 2 K X 16 RAM As shown in Figure 2-7, the 2 K X 16 RAM is divided into the following three major sections. • • •
1'-11 work space Device control block Sector buffer
This RAM can be accessed by both the 1'-11 chip and the high-speed controller. 2.15 DISK DRIVE CONTROL REGISTER AND STATUS BUFFER The disk drive control register and status buffer are shown in Figure 2-9. Under T -11 control, the disk drive control register provides drive selection and head control, including cylinder seeks on the selected drive. This register also contains static control information for the PLL and serializer. The drive status buffer is designed to interface the selected drive status to the DAL bus so that it can be interrogated by either the 1'-11 chip or the high-speed controller.
2-12
£l-Z
}~
-
INDEX(L)
INDEX(L)
Lr-
TRACKOO(L)
""' ..r
WRTFAULT(L)
.r
READY(L)
..r
ENDRVSTAT(L)
"'"
I'"
~
SEEKCPLT(L)
....,
DRVSL1ACK(L)
.r
DRVSLOACK(L) , ;
~
I
~
~
~~
...aC.
TIMEUP(HI
---.c "r"" ~
:IJ
m
» 0
.."
fiQ'
c::
@ N I \0
0
r;;'
You must respond to this prompt with a command to run the program. For example: DR>START
(default will cause the program to run one pass)
You are then asked the following. CHANGE HW (L) ? N CHANGE SW (L) ? N ENTER UNIT TO BE FORMATTED (D) ? X
(where X is the unit number assigned to the drive to be formatted)
USE EXISTING BAD BLOCK INFORMA T]ON (L) N ? N USE DOWN LINE LOAD (L) N ? N CONTINUE IF BAD BLOCK INFORMATION IS INACCURATE (L) N ? Y ENTER 8 CHARACTER SERIAL NUMBER (A) ?
6-3
The 8-character serial number is a unique serial number assigned to each RD51 disk drive. It is labeled on the left side of the disk drive (refer to Figure 6-4).
MR-11296
Figure 6-4
RD51 Serial Number Label Location
ENTER DATE IN MM-DD-YY FORMAT (A)? As shown above, the current date should be entered. The format routine takes approximately II minutes to complete, and its successful completion results in a message similar to the following. FORMAT COMPLETED, X REVECTORED LBNS RDRX EOP 1 o TOTAL ERRS The RQDX 1 controller module automatically revectors any bad sectors and prints the total number of revectored sectors in the format completed message. The maximum number of sectors that will be revectored is 144. If the formatting process is not successful, an error message appears on the terminal. Refer to the individual program listing to use this message (if necessary) to isolate the failure or to determine which FRU to replace. 6.3 RX50 DISKETTE DRIVE The RX50 diskette drive is shown in Figure 6-5. The RX50 diskette drive is a field replaceable unit (FRU) that is installed in a system mounting box. One cable connects the RX50 to the RQDX 1 controller module (via the distribution panel), another cable connects the drive to the power supply. There are no field alignment procedures for the RX50 diskette drive, since it is adjusted and aligned at the time of manufacture.
6-4
MR-9532
Figure 6-5
RX50 Diskette Drive
The RX50 diskette drive is a random access, dual-diskette storage device. It has two access doors and slots for diskette insertion and removal. An active drive light for each diskette slot informs you when that drive is busy. The RX50 diskette drive capacity is 800 K bytes of formatted data on two single-sided diskettes. This is accomplished by utilizing a 133.4 mm (5.25 inch) RX50K diskette that contains 80 tracks, 10 sectors per track, and 512 bytes per sector of modific;:d frequency modulation (MFM) data. The average access time, including latency, is 264 ms.
6-5
APPENDIX A RQDXl CONTROLLER MODULE BACKPLANE PIN ASSIGNMENTS
Diigital Equipment Corporation's plug-in modules, including the RQDXI controller module, all use the same contact (pin) identification system. Figure A-I shows the contact finger identification for a typical quad-height module. Each connector contains 36 lines (18 lines on each side of the printed circuit board). Table A-I lists the backplane pin assignments for the RQDX I controller module.
ROW A
BAl
ROW B
ROWC
DAl
SIDE 1 COMPONENT SIDE
SIDE 2 SOLDER SIDE ROW 0
Figure A-I
Quad Module Contact Finger Identification A-I
Table A-I
RQDXI Controller Module Backplane Pin Assignments
Pin
Signal Name
Pin
Signal Name
AAI ABI ACI ADI AEI AFI AHI AJI AKI ALI AMI ANI API ARI ASI AT1 AUI AVI
(BIRQS L) (BIRQ6 L) BDALl6 L BDAL17 L (SSPAREI or +SB) (SSPARE2) (SSPARE3) GND (MSPAREA) (MSPAREB) GND BDMR L (BHALT L) BREF L (+12Bor+SB) GND (PSPAREI) (+SB)
AA2 AB2 AC2 AD2 AE2 AF2 AH2 AJ2 AK2 AL2 AM2 AN2 AP2 AR2 AS2 AT2 AU2 AV2
+SV (-12V) GND (+12V) BDOUT L BRPLY L BDIN L BSYNC L BWTBT L BIRQ4 L BIAKI L BIAKO L BBS7 L BDMGI L BDMGO L BINIT L BDALO L BDALI L
BAI BBI BCI BDI BEl BFI BHI BJI BKI BLI BMI BNI BPI BRI BSI BTl BUI BYI
(BDCOK H) BPOK H BDALI8 L BDALI9 L BDAL20 L BDAL21 L (SSPARE8) GND (MSPAREB) (MSPAREB) GND BSACK L (BIRQ7 L) (BEVNT L) (+12B) GND (PSPARE2) +SY
BA2 BB2 BC2 BD2 BE2 BF2 BH2 BJ2 BK2 BL2 BM2 BN2 BP2 BR2 BS2 BT2 BU2 BV2
+SV (-12V) GND +12V BDAL2 L BDAL3 L BDAL4 L BDALS L BDAL6 L BDAL7 L BDAL8 L BDAL9 L BDALIO L BDALll L BDALl2 L BDAL13 L BDALl4 L BDALIS L
A-2
Table A-I
RQDXI Controller
ModulE~
Backplane Pin Assignments (Cont)
Pin
Signal Name
Pin
Signal Name
CAl CBI CCI COl CEI CFI CHI CJI CKI CLI CMI CNI CPI CRI CSI CTI CUI CVI
(Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) GND (Unused) (Unused) GND (Unused) (Unused) (Unused) (Unused) GND (Unused) (Unused)
CA2 CB2 CC2 CD2 CE2 CF2 CH2 CJ2 CK2 CL2 CM2 CN2 CP2 CR2 CS2 CT2 CU2 CV2
+5V (Unused) GND (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) CIAKI L CIAKO L (Unused) CDMGI L CDMGOL (Unused) (Unused) (Unused)
DAI OBI DCI DOl DEI DFI DHI DJI DKI DLI DMI DNI DPI DRI DSI DTI DUI DVI
(Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) GND (Unused) (Unused) GND (Unused) (Unused) (Unused) (Unused) GND (Unused) (Unused)
DA2 DB2 DC2 DD2 DE2 DF2 DH2 DJ2 DK2 DL2 DM2 DN2 DP2 DR2 DS2 DT2 DU2 DV2
+5V (Unused) GND (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused) (Unused)
A-3
APPENDIX B RQDXl CONTRC)LLER MODULE CABLE SIGNALS
Table 8-1 lists the RQDX I controller module signals on the J 1 connector.
Table B-1
Jl Coolnector Signals
Jl Pin
Signal Name
I
MFMWR TDT 1 (H) (RD51 only signal) MFMWRTDTI (L) (RD51 only signal) GROUND HEAD SEL 2 (L) (RDXX only signal)* GROUND SEEKCPLT (L) (RD51 only signal) RD 1 RDY (H) (RD51 only signal) WRT FAULT (L) DRV8USOE (L)
2 3 4 5
6 7 8
9 10 1I 12 13 14 15 16 17 18 19
20 21
22 23 24
25 26 27 28 29
* Reserved
HEAD SEL ] (L) (RD51 only signal) RXOWPTLED (L) (RX50 only signal) RDO RDY (H) (RD51 only signal) RX 1WPTLED (L) (RX50 only signal) DRVSLOACK (L) (RD51 only signal) MFMRDDATO (H) (RD51 only signal) MFMRDDA TO (L) (RD51 only signal) MFMWRTDTO (H) (RD51 only signal) MFMWRTDTO (L) (RD51 only signal) MFMRDDATI (H) (RD51 only signal) MFMRDDA Tl (L) (RD51 only signal) GROUND REDUCWRTI (L) RDOWRTPRO (L) (RD51 only signal) DRV SEL 4 (L) GROUND INDEX (L) RDI WRTPRO (L) (RD51 only signal) DRV SEL 1 (L) DRV SEL 2 (L) for future use.
B-1
Table B-1
J 1 Connector Signals (Cont)
Jl Pin
Signal Name
30 31 32 33 34 35 36 37 38 39
DRV SEL 3 (L) RX2WPTLED (L) (RX50 only signal) RXMOTORON (L) (RX50 only signal) GROUND DIRECTION (L) GROUND STEP (L) GROUND RXWRTDAT A (L) (RX50 only signal) GROUND
40
WRT GATE (L) GROUND TRACK 00 (L) RX3WPTLED (L) (RX50 only signal) DRVSLIACK (L) (RD51 only signal) GROUND READ DATA (L) (RX50 only signal) GROUND HEAD SEL 0 (L) GROUND READY (L)
41
42 43 44 45 46 47 48 49
50
* Reserved
for future usc.
B-2
APPENDIX C DISK DRIVE CABLE: CONNECTOR PIN ASSIGNMENTS
C.l RD51 DISK DRIVE CONNECTOR PIN ASSIGNMENTS The connector pin assignments for the RD51 disk drive signal and power cables are listed in Tables C-I through C-3.
Table C-l
RD51 Disk Drive Jl Siignal Connector Pin Assignments
GND Return Pin I 3 5 7 9
I1 13 15 17 19 21 23 25 27 29 31 33
Signal Pin
2
Signal Name Reserved Head Select 2 Write Gate Seek Complete Track 0 Write Fault Head Select 0 Reserved (to J2 pin 7) Head Select 1 Index Ready Step Drive Select 1 Drive Select 2 Drive Select 3 Drive Select 4 Direction In
4 6 8 10 12 14 16 18 20
22 24 26
28 30 32 34
C-l
Table C-2
RD51 Disk Drive J2 Signal Connector Pin Assignments
GND Return Pin 2 4 6 8
Signal Pin
Signal Name
1 3
Drive Selected Reserved Reserved Reserved (to J 1 pin 16) Reserved GND +MFM Write Data -MFM Write Data GND +MFM Read Data -MFM Read Data GND
5 7 9, 10 11 13 14 15 17 18 19
12 16
20
Table C-3
RD51 Disk Drive J3 Power Connector Pin Assignments GND Return Pin
Signal Pin
Signal Name
2 3
1
+12 V
4
+5 V
C-2
C.2 RX50 DISKETTE DRIVE CONNECTOR PIN ASSIGNMENTS The connector pin assignments for the RXSO diskette drive signal and power cables are listed in Tables C4 and C-S.
Table C-4
RX50 Diskette Drive J 1 Connector Pin Assignments
2
I 3 S 7 9 II 13 IS 17 19 21 23
TK43L (controls write current level) Reserved Drive Select 3 L Index L Drive Select 0 L Drive Select 1 L Drive Select 2 L Motor On L Direction (head movement direction) Step L (head movement distance) Write Data L Write Gate L Track 0 L Write Protect L Read Data L Reserved Ready L
4 6 8 10 12 14 16 18 20
22 24 26
2S 27
28
29
30 32 34
31 33
Table C-5
Signal Name
Signal Pin
GND Return Pin
RX50 Diskette Drive J3 Power Connector Pin Assignments GND Return Pin
Silgnal Pin
Signal Name
2
1 4
+S V
3
C-3
+12 V
Digital Equipment C-orporation • Bedford, MA 01730
